Folded instruction fetch pipeline
An instruction fetch pipeline includes first, second, and third sub-pipelines that respectively include: a TLB that receives a fetch virtual address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a predicted set index, and a data RAM that receives the predicted set index and a predicted way number that specifies a way of the entry from which a block of instructions was previously fetched. The predicted set index specifies the instruction cache set that includes the entry. The three sub-pipelines respectively initiate in parallel: a TLB access using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag, a tag RAM access using the predicted set index to read a set of tags, and a data RAM access using the predicted set index and the predicted way number to fetch the block of instructions.
1. An instruction fetch pipeline, comprising:
a first sub-pipeline that includes a translation lookaside buffer (TLB) configured to receive a fetch virtual address;
a second sub-pipeline that includes a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache configured to receive a predicted set index, wherein the predicted set index specifies a set of the instruction cache that includes an entry from which a block of instructions specified by the fetch virtual address was previously fetched; and
a third sub-pipeline that includes a data RAM of the instruction cache configured to receive the predicted set index and a predicted way number that specifies a way of the entry from which the block of instructions was previously fetched;
wherein the first, second and third sub-pipelines are configured to respectively initiate in parallel:
access of the TLB using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag;
access of the tag RAM using the predicted set index to read a set of tags; and
access of the data RAM using the predicted set index and the predicted way number to fetch the block of instructions.
2. The instruction fetch pipeline of claim 1 ,
wherein the predicted way number and the predicted set index are provided by a branch target buffer (BTB) in response to a lookup based on the fetch virtual address.
3. The instruction fetch pipeline of claim 2 ,
wherein the fetch physical address includes a correct set index; and
wherein the first sub-pipeline is further configured to check correctness of the predicted set index against the correct set index.
4. The instruction fetch pipeline of claim 3 ,
wherein when the predicted set index is incorrect, the correct set index is used to update an entry of a branch target buffer (BTB) that mispredicted the predicted set index.
5. The instruction fetch pipeline of claim 1 ,
wherein the second sub-pipeline is further configured to compare the tag with the set of tags read from the tag RAM to determine a correct way number.
6. The instruction fetch pipeline of claim 5 ,
wherein the second sub-pipeline is further configured to check correctness of the predicted way number against the correct way number.
7. The instruction fetch pipeline of claim 6 ,
wherein when the predicted way number is incorrect, the correct way number is used to update an entry of a branch target buffer (BTB) that mispredicted the predicted way number.
8. The instruction fetch pipeline of claim 1 ,
wherein the data RAM comprises a single-ported RAM and the tag RAM comprises a single-ported RAM.
9. The instruction fetch pipeline of claim 1 ,
wherein the TLB comprises a single-ported RAM.
10. A method, comprising:
in an instruction fetch pipeline that includes:
a first sub-pipeline that includes a translation lookaside buffer (TLB) configured to receive a fetch virtual address;
a second sub-pipeline that includes a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache configured to receive a predicted set index, wherein the predicted set index specifies a set of the instruction cache that includes an entry from which a block of instructions specified by the fetch virtual address was previously fetched; and
a third sub-pipeline that includes a data RAM of the instruction cache configured to receive the predicted set index and a predicted way number that specifies a way of the entry from which the block of instructions was previously fetched:
initiating, by the first, second and third sub-pipelines, respectively, in parallel:
access of the TLB using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag;
access of the tag RAM using the predicted set index to read a set of tags; and
access of the data RAM using the predicted set index and the predicted way number to fetch the block of instructions.
11. The method of claim 10 , further comprising:
providing, by a branch target buffer (BTB), the predicted way number and the predicted set index are provided by in response to a lookup based on the fetch virtual address.
12. The method of claim 11 , further comprising:
wherein the fetch physical address includes a correct set index; and
checking, by the first sub-pipeline, correctness of the predicted set index against the correct set index.
13. The method of claim 12 , further comprising:
when the predicted set index is incorrect, using the correct set index to update an entry of a branch target buffer (BTB) that mispredicted the predicted set index.
14. The method of claim 10 , further comprising:
comparing, by the second sub-pipeline, the tag with the set of tags read from the tag RAM to determine a correct way number.
15. The method of claim 14 , further comprising:
checking, by the second sub-pipeline, correctness of the predicted way number against the correct way number.
16. The method of claim 15 , further comprising:
when the predicted way number is incorrect, using the correct way number to update an entry of a branch target buffer (BTB) that mispredicted the predicted way number.
17. The method of claim 10 ,
wherein the data RAM comprises a single-ported RAM and the tag RAM comprises a single-ported RAM.
18. The method of claim 10 ,
wherein the TLB comprises a single-ported RAM.
19. A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring an instruction fetch pipeline comprising:
a first sub-pipeline that includes a translation lookaside buffer (TLB) configured to receive a fetch virtual address;
a second sub-pipeline that includes a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache configured to receive a predicted set index, wherein the predicted set index specifies a set of the instruction cache that includes an entry from which a block of instructions specified by the fetch virtual address was previously fetched; and
a third sub-pipeline that includes a data RAM of the instruction cache configured to receive the predicted set index and a predicted way number that specifies a way of the entry from which the block of instructions was previously fetched;
wherein the first, second and third sub-pipelines are configured to respectively initiate in parallel:
access of the TLB using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag;
access of the tag RAM using the predicted set index to read a set of tags; and
access of the data RAM using the predicted set index and the predicted way number to fetch the block of instructions.
20. The non-transitory computer-readable medium of claim 19 ,
wherein the predicted way number and the predicted set index are provided by a branch target buffer (BTB) in response to a lookup based on the fetch virtual address.