IP Library Granted Patent US 12,019,921
Granted Patent B2
US 12,019,921 · App. 18/129,191 · Granted Jun 25, 2024

Apparatus for processing received data

Inventors: Nagamasa Mizushima (Tokyo, JP); Kentaro Shimada (Tokyo, JP)
Assignee: HITACHI, LTD.
G06F3/0659G06F3/0604G06F3/0679G06F7/523H03M7/3084H03M7/6005
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Quick Facts
Patent No.
US 12,019,921
App. No.
18/129,191
Granted
Jun 25, 2024
Kind
B2
Abstract

To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.

Claims (42)

1. An apparatus for processing received data, the apparatus comprising:

a circuit configured to receive an input code compressed based on a range code; and

a decompression circuit configured to decompress a part or all of the input code to decode an N-bit string, wherein

N represents an integer greater than 1, and K represents an integer from 1 to N,

a bit value of a K-th bit of the input code is decoded based on a bit history of a bit before the K-th bit, and

the decompression circuit is configured to calculate a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of the bit before the K-th bit for a plurality of bits.

2. The apparatus according to claim 1 , wherein the decompression circuit is configured to repeatedly select a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.

3. The apparatus according to claim 1 , wherein the decompression circuit is configured to calculate the plurality of candidate bit values for each bit of the N-bit string based on the plurality of possible bit histories of the bit before the K-th bit in parallel for three or more bits.

4. The apparatus according to claim 3 , wherein, in calculating the plurality of candidate bit values in parallel for three or more bits, a number of the candidate bit values for a (K+1)-th bit is twice a number of the K-th bit.

5. The apparatus according to claim 1 , wherein

the decompression circuit is configured to

store probability values of a bit value appearing in accordance with the bit history, and

select and update a probability value corresponding to a bit history based on correct bits constituting the decoded N-bit string from the stored probability values.

6. The apparatus according to claim 1 , wherein

in calculation of the candidate bit values of the K-th bit in the N-bit string, multiplication of a division target range by probability values of 2{circumflex over ( )}(K−1) bit histories is performed to divide the division target range into two sections, and each of 2{circumflex over ( )}(K−1) Candidate bit values is determined from a section specified by a sub-code among the two sections of the K-th bit in the input code.

7. The apparatus according to claim 1 , wherein

when the number of bits to be decoded from the entire input code is larger than a preset maximum value, the decompression circuit performs decoding of a bit string based on a part of the input code for a plurality of cycles.

8. The apparatus according to claim 7 , wherein

in a second and subsequent cycles of the plurality of cycles, a division target range for determining each of the candidate bit values of the K-th bit is a section corresponding to a correct bit value of the K-th bit in an immediately preceding cycle.

9. A storage system, comprising:

an interface configured to receive a request from a host; and

a controller configured to execute writing of data to a storage drive and reading of data from the storage drive in accordance with a command from the host, wherein

the controller includes the decompression circuit according to claim 1 ,

the controller is configured such that, in accordance with a read command from the host, the input code transferred from the storage drive is decoded by the decompression circuit to generate read data, and

the read data is replied to the host via the interface.

10. The storage system according to claim 9 , wherein

the decompression circuit is configured to

store probability values of a bit value appearing in accordance with the bit history, and

select and update a probability value of each of correct bit values constituting the decoded N-bit string from the stored probability values.

11. The storage system according to claim 9 , wherein

in calculation of the candidate bit values of the K-th bit in the N-bit string, multiplication of a division target range by probability values of 2{circumflex over ( )}(K−1) bit histories is performed to divide the division target range into two sections, and a candidate bit value is determined from each of 2{circumflex over ( )}(K−1) sections for a sub-code of the K-th bit in the input code.

12. The storage system according to claim 9 , wherein

when the number of bits to be decoded from the entire input code is larger than a preset maximum value, the decompression circuit performs decoding of a bit string based on a part of the input code for a plurality of cycles.

13. The storage system according to claim 12 , wherein

in a second and subsequent cycles of the plurality of cycles, a division target range for determining each of the candidate bit values of the K-th bit is a section corresponding to a correct bit value of the K-th bit in an immediately preceding cycle.

14. A method for processing received data in an apparatus including a decompression circuit, the method comprising:

receiving an input code compressed based on a range code; and

decompressing a part or all of the input code to decode an N-bit string by the decompression circuit, wherein

N represents an integer greater than 1, and K represents an integer from 1 to N,

wherein a bit value of a K-th bit of the input code is decoded based on a bit history of a bit before the K-th bit, and

wherein the decompressing includes

calculating a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of the bit before the K-th bit for a plurality of bits.

Assignments (1)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
Priority Claims (1)
JP 2020-208090 · Dec 16, 2020 · national
Continuity (3)
Continuation 17462549 · Aug 31, 2021
Continuation 17189396 · Mar 2, 2021
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