Preventing parasitic current during program operations in memory
The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.
1. An apparatus, comprising:
an access line;
a sense line; and
a memory cell, wherein the memory cell includes:
a transistor having a floating gate and a control gate, wherein the control gate of the transistor is coupled to the access line; and
a diode, wherein a cathode of the diode is coupled to the sense line and an anode of the diode is coupled to a node of the transistor.
2. The apparatus of claim 1 , wherein the memory cell includes an additional transistor, wherein:
a first node of the additional transistor is coupled to the sense line; and
a second node of the additional transistor is coupled to the floating gate of the transistor.
3. The apparatus of claim 1 , wherein:
the memory cell includes an additional transistor having a control gate, wherein the control gate of the additional transistor is coupled to the access line.
4. The apparatus of claim 1 , wherein the diode is in series with the sense line and the node of the transistor.
5. The apparatus of claim 1 , wherein the diode is a bipolar junction diode.
6. An apparatus, comprising:
a plurality of source lines;
a plurality of sense lines; and
an array of memory cells, wherein each respective memory cell of the array includes:
a transistor having a floating gate and a control gate; and
a diode, wherein a cathode of the diode is coupled to one of the plurality of sense lines and an anode of the diode is coupled to a node of the transistor; and
wherein an additional node of the transistor of each respective memory cell of the array is coupled to one of the plurality of source lines.
7. The apparatus of claim 6 , wherein each respective memory cell of the array includes an additional transistor having a control gate.
8. The apparatus of claim 6 , wherein the transistor of each respective memory cell of the array is a p-type metal-oxide-semiconductor (PMOS) transistor.
9. The apparatus of claim 6 , wherein an n-type material of the diode of each respective memory cell of the array is in contact with a p-type channel of the transistor of that respective memory cell.
10. A method of operating memory, comprising:
applying a voltage to a sense line of the memory, wherein:
the sense line is coupled to a cathode of a diode of a memory cell; and
an anode of the diode is coupled to a node of a transistor of the memory cell; and
applying an additional voltage to an access line of the memory, wherein the access line is coupled to a control gate of the transistor of the memory cell.
11. The method of claim 10 , wherein the voltage is applied to the sense line during a program operation being performed on the memory.
12. The method of claim 10 , wherein:
the sense line is coupled to a first node of an additional transistor of the memory cell; and
a second node of the additional transistor is coupled to a floating gate of the transistor.
13. The method of claim 10 , wherein the method includes preventing, by the diode of the memory cell, current from flowing from the sense line through the transistor of the memory cell while the voltage is being applied to the sense line.
14. The method of claim 10 , wherein the method includes selecting the memory cell by applying the voltage to the sense line.
15. The method of claim 10 , wherein the additional voltage is applied to the access line during a sense operation being performed on the memory.
16. The method of claim 10 , wherein the method includes allowing, by the diode of the memory cell, current to flow through the transistor of the memory cell to the sense line while the additional voltage is being applied to the access line.
17. The method of claim 10 , wherein the voltage applied to the sense line is 0 Volts.
18. An apparatus, comprising:
a sense line; and
a memory cell, wherein the memory cell includes:
a transistor having a floating gate and a control gate;
a diode, wherein a cathode of the diode is coupled to the sense line and an anode of the diode is coupled to a node of the transistor; and
an additional transistor, wherein:
a first node of the additional transistor is coupled to the sense line; and
a second node of the additional transistor is coupled to the floating gate of the transistor.