Cross-domain electrostatic discharge protection

1. A semiconductor device, comprising:

a semiconductor substrate

a first circuit block formed within the semiconductor substrate having an output node, the first circuit block including first electronic devices coupled to a first supply voltage node formed within the semiconductor substrate and a first reference voltage node formed within the semiconductor substrate;

a second circuit block formed within the semiconductor substrate having an input node coupled to the output node of the first circuit block, the second circuit block including second electronic devices coupled to a second supply voltage node formed within the semiconductor substrate and a second reference voltage node formed within the semiconductor substrate that is separated from the first reference voltage node;

a transistor pass gate formed within the semiconductor substrate having first and second current terminals; and

a clamp device formed within the semiconductor substrate and coupled to the input node of the second circuit block;

wherein the first current terminal of the pass gate is coupled to the output node of the first circuit block; the second current terminal of the pass gate is coupled to the input node of the second circuit block; and the output node of the first circuit block is coupled to the input node of the second circuit block via the pass gate;

wherein the pass gate is configured to provide a resistive path between the first current terminal and the second current terminal such that, when an amount of charge sufficient to cause an electrostatic discharge (ESD) event accumulates at the output node of the first circuit block, an electric potential difference between the input node of the second circuit block and the second reference voltage node of the second circuit block does not exceed a first predetermined threshold voltage; and

wherein the clamp device is configured to shunt ESD-induced current from the input node of the second circuit block to the second reference voltage node or the second supply voltage node when an electrical potential difference between the input node of the second circuit block and the second reference voltage node exceeds a second predetermined threshold voltage that is less than the first predetermined threshold voltage; and

wherein the pass gate includes:

a p-channel transistor having a control terminal that is electrically coupled to the second supply voltage node via a pull-up resistor formed within the semiconductor substrate or via a tie-high transistor circuit formed within the semiconductor substrate; or

an n-channel transistor having a control terminal that is electrically coupled to the second reference voltage node via a pull-down resistor formed within the semiconductor substrate or via a tie-low transistor circuit formed within the semiconductor substrate.

2. The semiconductor device of claim 1 ,

wherein the pass gate includes the p-channel transistor having a control terminal that is electrically coupled to the second supply voltage node.

3. The semiconductor device of claim 2 , wherein the control terminal of the p-channel transistor is coupled to the second supply voltage node via the pull-up resistor formed within the semiconductor substrate.

4. The semiconductor device of claim 2 , wherein the control terminal of the p-channel transistor is coupled to the second supply voltage node via the tie-high transistor circuit formed within the semiconductor substrate.

5. The semiconductor device of claim 1 ,

wherein the pass gate includes an n-channel transistor having a control terminal that is electrically coupled to the second reference voltage node.

6. The semiconductor device of claim 5 , wherein the control terminal of the n-channel transistor of the pass gate is coupled to the second reference voltage node via the pull-down resistor formed within the semiconductor substrate.

7. The semiconductor device of claim 5 , wherein the control terminal of the n-channel transistor of the pass gate is coupled to the second reference voltage node via the tie-low transistor circuit formed within the semiconductor substrate.

8. The semiconductor device of claim 1 ,

wherein the pass gate includes the p-channel transistor having a control terminal that is electrically coupled to the second supply voltage node; and

wherein the pass gate also includes the n-channel transistor having a control terminal that is electrically coupled to the second reference voltage node; and

wherein the p-channel transistor of the pass gate is connected in parallel with the n-channel transistor in between the first current terminal and the second current terminal of the pass gate.

9. A semiconductor device, comprising:

a semiconductor substrate

a first circuit block formed within the semiconductor substrate having an output node, the first circuit block including first electronic devices coupled to a first supply voltage node formed within the semiconductor substrate and a first reference voltage node formed within the semiconductor substrate;

a second circuit block formed within the semiconductor substrate having an input node coupled to the output node of the first circuit block, the second circuit block including second electronic devices coupled to a second supply voltage node formed within the semiconductor substrate and a second reference voltage node formed within the semiconductor substrate that is separated from the first reference voltage node;

a transistor pass gate formed within the semiconductor substrate having first and second current terminals; and

a clamp device formed within the semiconductor substrate and coupled to the input node of the second circuit block;

wherein the first current terminal of the pass gate is coupled to the output node of the first circuit block; the second current terminal of the pass gate is coupled to the input node of the second circuit block; and the output node of the first circuit block is coupled to the input node of the second circuit block via the pass gate;

wherein the pass gate is configured to provide a resistive path between the first current terminal and the second current terminal such that, when an amount of charge sufficient to cause an electrostatic discharge (ESD) event accumulates at the output node of the first circuit block, an electric potential difference between the input node of the second circuit block and the second reference voltage node of the second circuit block does not exceed a first predetermined threshold voltage;

wherein the clamp device is configured to shunt ESD-induced current from the input node of the second circuit block to the second reference voltage node or the second supply voltage node when an electrical potential difference between the input node of the second circuit block and the second reference voltage node exceeds a second predetermined threshold voltage that is less than the first predetermined threshold voltage;

wherein the second circuit block includes digital logic circuitry having a first set of transistors of a first conduction type, wherein each transistor of the first set of transistors is defined by a first set of transistor characteristics; and

wherein the pass gate includes a second set of transistors of the first conduction type that are also defined by the first set of transistor characteristics.

10. The semiconductor device of claim 9 ,

wherein the first set of transistors of the first conduction type is a set of n-channel transistors and the second set of transistors of the first conduction type is also set of n-channel transistors; and

wherein the digital logic circuitry of the second circuit block further comprises a first set of p-channel transistors, each of which is defined by a second set of transistor characteristics; and

wherein the pass gate further includes:

a second set of p-channel transistors, each of which is also defined by the second set of transistor characteristics.

11. A method of fabricating a semiconductor device, the method comprising:

forming a transistor pass gate having first and second current terminals within a semiconductor substrate;

electrically coupling the first current terminal of the pass gate to an output node of a first circuit block formed within the semiconductor substrate;

electrically coupling the second current terminal of the pass gate to an input node of a second circuit block formed within the semiconductor substrate; and

forming a clamp device within the semiconductor substrate that is coupled to the input node of the second circuit block;

wherein the first circuit block includes first electronic devices coupled to a first supply voltage node formed within the semiconductor substrate and a first reference voltage node formed within the semiconductor substrate;

wherein the input node of the second circuit block is coupled to the output node of the first circuit block via the pass gate and the second circuit block includes second electronic devices coupled to a second supply voltage node formed within the semiconductor substrate and a second reference voltage node formed within the semiconductor substrate that is separated from the first reference voltage node;

wherein the pass gate is configured to provide a resistive path between the first current terminal and the second current terminal such that, when an amount of charge sufficient to cause an electrostatic discharge (ESD) event accumulates at the output node of the first circuit block, an electric potential difference between the input node of the second circuit block and the second reference voltage node of the second circuit block does not exceed a first predetermined threshold voltage;

wherein the clamp device is configured to shunt ESD-induced current from the input node of the second circuit block to the second reference voltage node or the second supply voltage node when an electrical potential difference between the input node of the second circuit block and the second reference voltage node exceeds a second predetermined threshold voltage that is less than the first predetermined threshold voltage; and

wherein the forming the pass gate comprises:

forming a p-channel transistor within the semiconductor substrate and electrically coupling a control terminal of the p-channel transistor to the second supply voltage node via a polysilicon pull-up resistor formed within the semiconductor substrate or via a tie-high transistor circuit formed within the semiconductor substrate; or

forming an n-channel transistor within the semiconductor substrate and electrically coupling a control terminal of the n-channel transistor to the second reference voltage node via a polysilicon pull-down resistor formed within the semiconductor substrate or via a tie-low transistor circuit formed within the semiconductor substrate.

12. The method of claim 11 ,

wherein forming the pass gate includes forming the p-channel transistor within the semiconductor substrate; and

wherein the method further comprises electrically coupling the control terminal of the p-channel transistor to the second supply voltage node.

13. The method of claim 12 , further comprising electrically coupling the control terminal of the p-channel transistor is coupled to the second supply voltage node via the polysilicon pull-up resistor formed within the semiconductor substrate.

14. The method of claim 12 , further comprising electrically coupling the control terminal of the p-channel transistor is coupled to the second supply voltage node via the tie-high transistor circuit formed within the semiconductor substrate.

15. The method of claim 11 ,

wherein forming the pass gate includes forming the n-channel transistor within the semiconductor substrate; and

wherein the method further comprises electrically coupling the control terminal of the n-channel transistor to the second reference voltage node.

16. The method of claim 15 , further comprising electrically coupling the control terminal of the n-channel transistor to the second reference voltage node via the pull-down resistor formed within the semiconductor substrate.

17. The method of claim 15 , further comprising electrically coupling the control terminal of the n-channel transistor to the second reference voltage node via the tie-low transistor circuit formed within the semiconductor substrate.

18. The method of claim 11 , wherein forming the pass gate comprises:

forming the p-channel transistor as part of the pass gate and electrically coupling the control terminal of the p-channel transistor to the second supply voltage node; and

forming the n-channel transistor as part of the pass gate and electrically coupling the control terminal of the n-channel transistor to the second reference voltage node; and

wherein the p-channel transistor is connected in parallel with the n-channel transistor in between the first current terminal and the second current terminal of the pass gate.

19. A method of forming a semiconductor device, comprising:

forming a transistor pass gate having first and second current terminals within a semiconductor substrate;

electrically coupling the first current terminal of the pass gate to an output node of a first circuit block formed within the semiconductor substrate;

electrically coupling the second current terminal of the pass gate to an input node of a second circuit block formed within the semiconductor substrate; and

forming a clamp device within the semiconductor substrate that is coupled to the input node of the second circuit block;

wherein the first circuit block includes first electronic devices coupled to a first supply voltage node formed within the semiconductor substrate and a first reference voltage node formed within the semiconductor substrate;

wherein the input node of the second circuit block is coupled to the output node of the first circuit block via the pass gate and the second circuit block includes second electronic devices coupled to a second supply voltage node formed within the semiconductor substrate and a second reference voltage node formed within the semiconductor substrate that is separated from the first reference voltage node;

wherein the pass gate is configured to provide a resistive path between the first current terminal and the second current terminal such that, when an amount of charge sufficient to cause an electrostatic discharge (ESD) event accumulates at the output node of the first circuit block, an electric potential difference between the input node of the second circuit block and the second reference voltage node of the second circuit block does not exceed a first predetermined threshold voltage;

wherein the clamp device is configured to shunt ESD-induced current from the input node of the second circuit block to the second reference voltage node or the second supply voltage node when an electrical potential difference between the input node of the second circuit block and the second reference voltage node exceeds a second predetermined threshold voltage that is less than the first predetermined threshold voltage;

wherein the second circuit block includes digital logic circuitry comprising a first set of transistors of a first conduction type, wherein each transistor of the first set of transistors is defined by a first set of transistor characteristics; and

wherein the method further comprises forming, as part of the pass gate, a second set of transistors of the first conduction type within the semiconductor substrate that are also defined by the first set of transistor characteristics.

20. The method of claim 19 ,

wherein the first set of transistors of the first conduction type is a first set of n-channel transistors, each of which is defined by a first set of transistor characteristics;

wherein the second circuit block further includes a first set of p-channel transistors, each of which is defined by a second set of transistor characteristics;

wherein the second set of transistors of the first conduction type is a second set of n-channel transistors, each of which is also defined by the first set of transistor characteristics; and

wherein the method further comprises forming, as parts of the pass gate, a second set of p-channel transistors, each of which is also defined by the second set of transistor characteristics.