Physically unclonable function (PUF) generation

1. A physically unclonable function (PUF) generator, comprising:

a first transistor connected to a power supply voltage and having a first predetermined threshold voltage (VT);

a second transistor connected to the power supply voltage and having the first predetermined VT, wherein the first transistor provides a first output signal and the second transistor provides a second output signal for generating a PUF signature based on differences in turn on times of the first transistor and the second transistor; and

an amplifier including a plurality of transistors each having a second predetermined VT that is different than the first predetermined VT and having a first input connected to receive the first output signal and a second input connected to receive the second output signal and configured to output the PUF signature.

2. The PUF generator of claim 1 , further comprising a plurality of the first transistors and a plurality of the second transistors, wherein the amplifier is configured to receive the first output signal of each of the plurality of the first transistors.

3. The PUF generator of claim 2 , further comprising a plurality of the amplifiers, wherein each of the amplifiers is configured to output a respective bit of the PUF signature.

4. The PUF generator of claim 1 , further comprising a plurality of the first transistors, a plurality of the second transistors, and a plurality of the amplifiers, wherein each of the plurality of the first transistors and each of the plurality of the second transistors is connected to one of the plurality of the amplifiers and each of the plurality of the amplifiers is configured to output a respective bit of the PUF signature.

5. The PUF generator of claim 1 , further comprising a pre-discharge circuit coupled to the first transistor and configured to set the first output signal to a predetermined value.

6. The PUF generator of claim 1 , further comprising a pre-discharge circuit including a first NMOS transistor and a second NMOS transistor configured to selectively connect a first bit line and a second bit line, respectively, to ground.

7. The PUF generator of claim 1 , wherein the first transistor and the second transistor are PMOS transistors.

8. The PUF generator of claim 1 , wherein the first predetermined VT is higher than the second predetermined VT.

9. The PUF generator of claim 1 , wherein the first predetermined VT is a high threshold voltage (HVT).

10. The PUF generator of claim 1 , wherein the second predetermined VT is a low threshold voltage (LVT).

11. The PUF generator of claim 1 , further comprising a timing circuit connected between the amplifier and gates of the first transistor and the second transistor, the timing circuit configured to bias the first transistor and the second transistor in response to the first output signal and the second output signal.

12. The PUF generator of claim 1 , further comprising first and second bit lines and a word line, wherein the first transistor is connected between the power supply voltage and the first bit line, the second transistor is connected between the power supply voltage and the second bit line, and gates of the first transistor and the second transistor are connected to the word line.

13. A circuit, comprising:

a first inverter including a first PMOS transistor having a first predetermined voltage threshold (VT) and connected to a first NMOS transistor having a second predetermined VT that is different than the first predetermined VT; and

a second inverter including a second PMOS transistor having the first predetermined VT and connected to a second NMOS transistor having the second predetermined VT,

wherein the first inverter and the second inverter are cross-coupled inverters that generate a physically unclonable function (PUF) bit based on differences in turn on times of the first inverter and the second inverter.

14. The circuit of claim 13 , wherein the first predetermined VT is a standard threshold voltage (SVT), and the second predetermined VT is a high threshold voltage (HVT).

15. The circuit of claim 13 , wherein the first and second PMOS transistors are configured to provide first and second complementary output signals on respective first and second bit lines for generating a PUF signature based on the differences in turn on times of the first inverter and the second inverter.

16. The circuit of claim 13 , further comprising:

a third PMOS transistor having the first predetermined VT and connected between a power supply terminal and the first PMOS transistor and between the power supply terminal and the second PMOS transistor.

17. A method of providing a physically unclonable function (PUF) signature, the method comprising:

providing a first transistor and a second transistor each having a first predetermined threshold voltage (VT);

providing a first output signal for generating the PUF signature based on differences in turn on times of the first transistor and the second transistor;

amplifying the first output signal by an amplifier including a plurality of transistors each having a second predetermined VT that is different than the first predetermined VT; and

outputting, by the amplifier, the PUF signature.

18. The method of claim 17 , further comprising:

providing a plurality of the first transistors;

providing a plurality of the second transistors; and

receiving each of the first output signals based on each of the plurality of the first transistors at the amplifier.

19. The method of claim 17 , further comprising:

providing a plurality of the first transistors;

providing a plurality of the second transistors;

providing a plurality of the amplifiers; and

receiving each of the first output signals based on each of the plurality of the first transistors at a different one of the plurality of the amplifiers.

20. The method of claim 17 , further comprising:

pre-discharging the first output signal to a predetermined value.