Push-pull buffer circuit
A buffer circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a load terminal. The control terminal is coupled to a preamplifier input terminal. The second transistor includes a first current terminal and a second current terminal. The first current terminal of the second transistor is coupled to the second current terminal of the first transistor. The third transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the third transistor is coupled to the load terminal. The second current terminal of the third transistor is coupled to a ground terminal. The control terminal of the third transistor is coupled to second current terminal of the second transistor.
1. A buffer circuit, comprising:
a first transistor, wherein the first transistor is an n-channel field effect transistor, the first transistor including:
a first current terminal coupled to a load terminal;
a second current terminal; and
a control terminal coupled to a preamplifier input terminal;
a second transistor, wherein the second transistor is a p-channel field effect transistor, the second transistor including:
a first current terminal coupled to the second current terminal of the first transistor; and
a second current terminal;
a third transistor, wherein the third transistor is an n-channel field effect transistor, the third transistor including:
a first current terminal coupled to the load terminal;
a second current terminal coupled to a ground terminal; and
a control terminal coupled to the second current terminal of the second transistor; and
a fourth transistor, wherein the fourth transistor is an n-channel field effect transistor, the fourth transistor including:
a first current terminal coupled to the second current terminal of the second transistor;
a second current terminal coupled to the ground terminal; and
a control terminal coupled to the second current terminal of the second transistor and the control terminal of the third transistor.
2. The buffer circuit of claim 1 , further comprising a constant current source coupled to the second current terminal of the first transistor and the first current terminal of the second transistor.
3. The buffer circuit of claim 2 , wherein the constant current source includes:
a fifth transistor including:
a first current terminal coupled to a power supply terminal;
a second current terminal coupled to a current source; and
a control terminal coupled to the second current terminal of the fifth transistor; and
a sixth transistor including:
a first current terminal coupled to the power supply terminal;
a second current terminal coupled to the second current terminal of the first transistor; and
a control terminal coupled to the control terminal of the fifth transistor.
4. The buffer circuit of claim 1 , wherein:
the second transistor includes a control terminal; and
the buffer circuit includes a bias voltage circuit coupled to the control terminal of the second transistor.
5. The buffer circuit of claim 4 , wherein the bias voltage circuit includes:
a fifth transistor including:
a first current terminal;
a second current terminal coupled to a current source; and
a control terminal coupled to the current source and the control terminal of the second transistor; and
a resistor coupled between a power supply terminal and the first current terminal of the fifth transistor.
6. A buffer circuit, comprising:
a first transistor, wherein the first transistor is an n-channel field effect transistor, the first transistor including:
a first current terminal coupled to a load terminal;
a second current terminal; and
a control terminal coupled to a preamplifier input terminal;
a second transistor, wherein the second transistor is a p-channel field effect transistor, the second transistor including:
a first current terminal coupled to the second current terminal of the first transistor; and
a second current terminal;
a third transistor, wherein the third transistor is an n-channel field effect transistor, the third transistor including:
a first current terminal coupled to a power supply terminal;
a second current terminal coupled to the second current terminal of the second transistor; and
a control terminal coupled to the second current terminal of the second transistor; and
a fourth transistor, wherein the fourth transistor is an n-channel field effect transistor, the fourth transistor including:
a first current terminal coupled to the power supply terminal;
a second current terminal coupled to the load terminal; and
a control terminal coupled to the control terminal of the third transistor.
7. The buffer circuit of claim 6 , further comprising a constant current source coupled to the second current terminal of the first transistor.
8. The buffer circuit of claim 6 , wherein:
the second transistor includes a control terminal; and
the buffer circuit includes a bias voltage circuit coupled to the control terminal of the second transistor.
9. A buffer circuit comprising:
a constant current source;
a common drain circuit configured to source current from the constant current source to a load terminal, wherein the common drain circuit includes:
a first transistor including:
a first current terminal coupled to the load terminal;
a second current terminal coupled to the constant current source; and
a control terminal coupled to a preamplifier terminal;
a common source circuit coupled to the load terminal, and configured to sink current from the load terminal, the common source circuit includes:
a second transistor including:
a first current terminal coupled to the load terminal;
a second current terminal coupled to a ground terminal; and
a control terminal;
a control transistor coupled between the constant current source and the common source circuit, and configured to control the common source circuit based on a current from the constant current source that bypasses the common drain circuit, the control transistor includes:
a first current terminal coupled to the constant current source; and
a second current terminal coupled to the control terminal of the second transistor; and
a current mirror circuit including:
the second transistor; and
a third transistor including:
a first current terminal coupled to the second current terminal of the control transistor;
a second current terminal coupled to the ground terminal; and
a control terminal coupled to the first current terminal of the third transistor and the control terminal of the second transistor; and
wherein:
the first transistor, the second transistor, and the third transistor are n-channel field effect transistors; and
the control transistor is a p-channel field effect transistor.
10. An amplifier circuit, comprising:
a preamplifier circuit including:
a feedback input; and
a preamp output; and
a buffer circuit including:
a first transistor, wherein the first transistor is an n-channel field effect transistor, the first transistor including:
a first current terminal coupled to the feedback input;
a second current terminal; and
a control terminal coupled to the preamp output;
a second transistor, wherein the second transistor is a p-channel field effect transistor, the second transistor including:
a first current terminal coupled to the second current terminal of the first transistor; and
a second current terminal;
a third transistor, wherein the third transistor is an n-channel field effect transistor, the third transistor including:
a first current terminal coupled to the feedback input;
a second current terminal coupled to a ground terminal; and
a control terminal coupled to second current terminal of the second transistor; and
a fourth transistor, wherein the fourth transistor is an n-channel field effect transistor, the fourth transistor including:
a first current terminal coupled to the second current terminal of the second transistor;
a second current terminal coupled to the ground terminal; and
a control terminal coupled to the second current terminal of the second transistor.
11. The amplifier circuit of claim 10 , further comprising a constant current source coupled to the second current terminal of the first transistor and the first current terminal of the second transistor.
12. The amplifier circuit of claim 10 , wherein:
the second transistor includes a control terminal; and
the buffer circuit includes a bias voltage circuit coupled to the control terminal of the second transistor.
13. The buffer circuit of claim 6 , wherein the first current terminal of the first transistor is directly connected to the load terminal.
14. The buffer circuit of claim 1 , wherein the first current terminal of the first transistor is directly connected to the load terminal.
15. The amplifier circuit of claim 10 , wherein the second current terminal of the first transistor is coupled to a load terminal.
16. The amplifier circuit of claim 15 , wherein the load terminal is adapted to be coupled to a universal serial bus (USB) connector.
17. The amplifier circuit of claim 15 , wherein the second current terminal is directly coupled to the load terminal.