Hybrid-cycle quantum-clock frequency regulation
An atomic clock employs hybrid long/short quantum clock frequency regulation wherein each of a series of regulation cycles includes a relatively long (four Ramsey-cycle) combination error signal (CES) cycle and plural relatively short (two Ramsey-cycle) single error signal (SES) cycles. The CES cycles provide for better long-term stability than can be provided using only SES cycles. However, including the SES cycles between CES cycles improves short term stability with negligible diminishment of long-term stability.
1. A quantum clock system comprising:
a electromagnetic radiation (EMR) source;
a clock frequency generator coupled to the EMR source so as to cause the EMR source to modulate EMR emitted by the EMR source;
quantum-state carriers (QSCs) defining a set of one or more resonant frequencies, the QSCs being optically coupled to the EMR source for being illuminated by modulated EMR therefrom;
a photodetector for measuring an optical characteristic of the QSCs after being illuminated by the EMR; and
a controller that implements a series of clock-frequency regulation cycles, each regulation cycle including at least one long adjustment cycle and plural short adjustment cycles, the controller being coupled to the clock frequency generator for adjusting a clock frequency output thereof in response to each long cycle and in response to each short cycle, each long cycle containing at least three measurement cycles, each short cycle including at most two measurement cycles, each measurement cycle involving a measurement by the photodetector.
2. The quantum clock system of claim 1 wherein a ratio of a number of short cycles to a number of long cycles is at least 3:1.
3. The quantum clock system of claim 1 wherein each regulation cycle includes exactly one long cycle, the long cycle being a combination error signal (CES) cycle and the short cycles being single error signal (SES) cycles.
4. The quantum clock system of claim 3 wherein a ratio of a number of SES cycles to a number of CES cycles is at least 3:1.
5. The quantum clock system of claim 3 wherein each CES cycle includes four measurement cycles, and each SES includes two measurement cycles, all measurement cycles being Ramsey cycles.
6. The quantum clock system of claim 5 wherein each Ramsey cycle is characterized by a detuning relative to a dark combination of resonant frequencies and an evolve time for the QSCs, each evolve time extending between an illumination of the QSCs and a fluorescence measurement of the QSCs, the Ramsey cycles for the CES cycle including:
a first red detuned illumination followed by a first relatively short evolve duration;
a blue-detuned illumination followed by a second relatively short evolve duration;
a second red detuned illumination followed by a first relatively long evolve duration; and
a blue detuned illumination followed by a second relatively long evolve duration.
7. The quantum clock system of claim 1 wherein the EMR source includes a laser for outputting a single-mode EMR and an electro-optical modulator (EOM) for converting the single-mode EMR to multi-mode EMR.
8. The quantum clock system of claim 1 wherein a clock frequency is in a microwave range.
9. A quantum clock frequency adjustment process comprising a series of regulation cycles, each of the regulation cycles including:
adjusting a quantum clock frequency of a quantum clock based on a long error-signal cycle, the long error-signal cycle including at least three measurement cycles; and
making plural quantum clock frequency adjustments of the quantum clock based on respective ones of consecutive short error signal cycles, each short signal error cycle including at most two measurement cycles.
10. The quantum clock frequency adjustment process of claim 9 wherein each regulation cycle includes exactly one long cycle.
11. The quantum clock frequency adjustment process of claim 10 where each regulation cycle includes at least three short cycles.
12. The quantum clock frequency adjustment process of claim 11 wherein each long cycle is a combination error signal (CES) cycle, each short cycle is a single-error signal (SES) cycle, and each of the measurement cycles is a Ramsey cycle.