Methods of forming microelectronic devices including source structures overlying stack structures

1. A method of forming a microelectronic device, comprising:

forming a microelectronic device structure comprising:

a base structure;

a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure;

a stack structure overlying the doped semiconductive structure and comprising a vertically alternating sequence of conductive structures and insulative structures;

cell pillar structures vertically extending through the stack structure and to the first portion of the doped semiconductive structure; and

digit line structures vertically overlying the stack structure;

forming an additional microelectronic device structure comprising control logic devices;

attaching the microelectronic device structure to the additional microelectronic device structure to form a microelectronic device structure assembly, the digit line structures vertically interposed between the stack structure and the control logic devices within the microelectronic device structure assembly;

removing the base structure and the second portions of the doped semiconductive structure to expose first portion of the doped semiconductive structure; and

patterning the first portion of the doped semiconductive structure after removing the base structure and the second portions of the doped semiconductive structure to form at least one source structure over the stack structure and coupled to the cell pillar structures.

2. The method of claim 1 , wherein forming a microelectronic device structure comprises forming the microelectronic device structure to further comprise conductive contact structures vertically extending through the stack structure and into the doped semiconductive structure.

3. The method of claim 1 , wherein forming a microelectronic device structure comprises:

forming a preliminary stack structure over a doped semiconductive material overlying the base structure, the preliminary stack structure comprising a vertically alternating sequence of first insulative structures and second insulative structures;

forming openings vertically extending through the preliminary stack structure and the doped semiconductive material and into the base structure;

filling lower portions of the openings positioned within the base structure and the doped semiconductive material with additional semiconductive material;

annealing the doped semiconductive material and the additional semiconductive material to form the doped semiconductive structure therefrom;

forming the cell pillar structures within remaining, upper portions of the openings;

forming slots extending through the preliminary stack structure;

at least partially replacing the second insulative structures with the conductive structures using the slots to form the stack structure, the insulative structures of the stack structure comprising remaining portions of the first insulative structures; and

forming the digit line structures over and in electrical communication with the cell pillar structures.

4. The method of claim 1 , wherein forming a microelectronic device structure comprises forming the microelectronic device structure to further comprise:

insulative line structures on the digit line structures;

digit line contact structures extending through portions of the insulative line structures and contacting the digit line structures; and

conductive pad structures on the digit line contact structures.

5. The method of claim 4 , wherein forming an additional microelectronic device structure comprises forming the microelectronic device structure to further comprise additional conductive pad structures over the control logic devices.

6. The method of claim 5 , wherein attaching the microelectronic device structure to the additional microelectronic device structure comprises:

vertically inverting one of the microelectronic device structure and the additional microelectronic device structure; and

bonding the conductive pad structures of the microelectronic device structure to the additional conductive pad structures of the additional microelectronic device structure.

7. The method of claim 1 , wherein removing the base structure and the second portions of the doped semiconductive structure to expose the first portion of the doped semiconductive structure comprises forming an upper surface of the first portion of the doped semiconductive structure to be substantially planar and vertically offset from the cell pillar structures.

8. The method of claim 1 , further comprising forming at least one metallic strapping material over the first portion of the doped semiconductive structure prior to patterning the first portion of the doped semiconductive structure.

9. The method of claim 1 , further comprising:

forming conductive routing structures over and in electrical communication with the at least one source structure; and

forming conductive pad structures over and in electrical communication with the conductive routing structures.

10. The method of claim 9 , further comprising forming at least one metal-insulator-metal (MIM) capacitor vertically over the at least one the source structure and vertically under the conductive routing structures.

11. The method of claim 9 , further comprising forming at least one metal-insulator-semiconductor (MIS) capacitor vertically under the conductive routing structures and at least partially vertically over the at least one the source structure.

12. A method of forming a microelectronic device, comprising:

forming a memory array wafer comprising:

doped semiconductive material comprising:

a region above a base structure; and

additional regions projecting into the base structure from the region;

a stack structure above the doped semiconductive material and comprising a conductive material vertically interleaved with insulative material;

strings of memory cells extending through the stack structure and to the region of the doped semiconductive material;

digit lines above the stack structure; and

dielectric material above the digit lines;

forming a control circuitry wafer separate from the memory array wafer and comprising:

control logic circuitry; and

additional dielectric material above the control logic circuitry;

bonding the dielectric material of the memory array wafer to the additional dielectric material of the control circuitry wafer to form an assembly;

removing the base structure and the additional regions of the doped semiconductive material to expose region of the doped semiconductive material; and

forming a source structure from some of the region of the doped semiconductive material after removing the base structure and the additional regions of the doped semiconductive material, the source structure coupled to the strings of memory cells.

13. The method of claim 12 , wherein:

forming a memory array wafer further comprises forming conductive bond pads extending through the dielectric material and to the digit lines; and

forming a control circuitry wafer separate from the memory array wafer further comprises forming additional conductive bond pads extending through the additional dielectric material and in electrical communication with the control logic circuitry.

14. The method of claim 13 , further comprising bonding the conductive bond pads of the memory array wafer to the additional conductive bond pads of the additional conductive bond pads.

15. The method of claim 12 , wherein forming a memory array wafer comprises:

forming a preliminary stack structure above doped epitaxial silicon, the preliminary stack structure comprising sacrificial material vertically interleaved with the insulative material;

forming openings extending through the preliminary stack structure and the doped epitaxial silicon and into the base structure;

forming additional epitaxial silicon in portions of the openings within vertical boundaries of the base structure and the doped epitaxial silicon;

annealing the doped epitaxial silicon and the additional epitaxial silicon to form the doped semiconductive material therefrom;

forming pillar structures individually comprising semiconductive material within portions of the openings remaining unfilled with the additional epitaxial silicon, the semiconductive material in contact with the doped semiconductive material;

forming slots extending through the preliminary stack structure;

replacing the sacrificial material with the conductive material after forming the slots to form the stack structure; and

forming the digit lines over the pillar structures after replacing the sacrificial material with the conductive material.

16. The method of claim 12 , further comprising:

forming the memory array wafer to further comprise a conductive contact structure horizontally offset from the strings of memory cells and extending completely through the stack structure and into the region of the doped semiconductive material; and

forming a contact pad from some other of the region of the doped semiconductive material after removing the base structure and the additional regions of the doped semiconductive material, the contact pad coupled to the conductive contact structure.

17. The method of claim 16 , wherein forming a contact pad from some other of the region of the doped semiconductive material comprises forming the contact pad and the source structure from the region of the doped semiconductive material substantially simultaneously, the contact pad electrically isolated from the source structure.

18. A method of forming a microelectronic device, comprising:

forming a first microelectronic device structure comprising:

a preliminary structure overlying a base structure and comprising conductively doped epitaxial silicon;

a stack structure overlying the preliminary structure and comprising conductive structures and insulative structures vertically alternating with the conductive structures;

pillar structures comprising semiconductive material vertically extending through the stack structure and into preliminary structure;

conductive contact structures horizontally offset from the pillar structures and vertically extending completely through the stack structure and into the preliminary structure; and

digit line structures vertically overlying the stack structure and in electrical communication with the pillar structures;

attaching the first microelectronic device structure to a second microelectronic device structure comprising control logic circuitry through a combination of oxide-oxide bonding and metal-metal bonding to form an assembly, the digit line structures of the assembly in electrical communication with the control logic circuitry of the assembly;

after forming the assembly, removing the base structure to expose the preliminary structure; and

after removing the base structure, patterning the preliminary structure to form at least one source structure coupled to the pillar structures and contact pads electrically isolated from the at least one source and coupled to the conductive contact structures.

19. The method of claim 18 , further comprising:

forming conductive contacts overlying and in electrical communication with the source structure;

forming conductive routing structures over and in electrical communication with the conductive contacts;

additional conductive contacts over and in electrical communication with the conductive routing structures; and

conductive pad structures over and in electrical communication with the additional conductive contacts.

20. The method of claim 19 , further comprising forming one or more of at least one metal-insulator-metal (MIM) capacitor and at least one metal-insulator-semiconductor (MIS) capacitor between the source structure and the conductive routing structures.