Semiconductor device with strain relaxed layer
A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
1. A semiconductor device comprising:
an epitaxial substrate comprising:
a substrate;
a strain-relaxed layer covering and contacting the substrate, wherein there is no stress in the strain-relaxed layer;
a III-V compound stacked layer covering and contacting the strain-relaxed layer, wherein the III-V compound stacked layer comprises aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride, and the III-V compound stacked layer is a multilayer epitaxial structure, and wherein the III-V compound stacked layer comprises a transition layer and a gradient layer disposed from bottom to top, the transition layer contacts the gradient layer, a chemical formula of the gradient layer is Al Z Ga 1-Z N, 0≤Z≤1, Z decreases from a bottom of the gradient layer to a top of the gradient layer, a chemical formula of an entirety of the transition layer is Al x Ga 1-x N, and 0.7≤X≤0.8;
an HEMT disposed on the epitaxial substrate, wherein the HEMT comprises:
a gallium nitride layer directly contacting the gradient layer; and
an aluminum gallium nitride layer disposed on and directly contacting the gallium nitride layer.
2. The semiconductor device of claim 1 , wherein the III-V compound stacked layer further comprises:
a nucleation layer disposed below the transition layer, and the nucleation layer covering and contacting the strain-relaxed layer, wherein the nucleation layer comprises aluminum nitride.
3. The semiconductor device of claim 1 , wherein the substrate comprises a silicon substrate, a sapphire substrate or a silicon on insulator substrate.
4. The semiconductor device of claim 1 , further comprising:
a source electrode and a drain electrode disposed on the aluminum gallium nitride layer; and
a gate electrode disposed between the source electrode and the drain electrode and on the aluminum gallium nitride layer.
5. The semiconductor device of claim 1 , wherein the strain-relaxed layer comprises a first strain-relaxed layer, and the first strain-relaxed layer comprises silicon oxide, silicon nitride or silicon carbide.
6. The semiconductor device of claim 5 , wherein the first strain-relaxed layer comprises a plurality of different material layers.
7. The semiconductor device of claim 5 , further comprising a plurality of the first strain-relaxed layers stacking and contacting each other.
8. The semiconductor device of claim 5 , wherein the strain-relaxed layer further comprises a second strain-relaxed layer contacting the first strain-relaxed layer, and the second strain-relaxed layer comprises silicon oxide, silicon nitride or silicon carbide.
9. The semiconductor device of claim 1 , wherein a thickness of the strain-relaxed layer is greater than 1 nanometer.