Latch-up prevention

1. A semiconductor device, comprising:

an active region including a channel region and a source/drain region adjacent the channel region;

an anti-punch-through (APT) implantation region over the channel region;

a plurality of nanostructures over the APT implantation region;

a gate structure over the APT implantation region and wrapping around each of the plurality of nanostructures;

a bottom dielectric feature over the source/drain region;

a germanium feature sandwiched directly between and in contact with the bottom dielectric feature and the source/drain region of the active region; and

a source/drain feature disposed on the bottom dielectric feature,

wherein the bottom dielectric feature comprises silicon germanium oxide,

wherein end surfaces of the plurality of nanostructures are in direct contact with a sidewall of the source/drain feature.

2. The semiconductor device of claim 1 , further comprising:

a plurality of inner spacer features interleaving the plurality of nanostructures; and

a dielectric layer disposed between a bottommost one of the plurality of inner spacer features and a sidewall of the bottom dielectric feature.

3. The semiconductor device of claim 2 , wherein the dielectric layer comprises silicon nitride, hafnium silicide, aluminum oxynitride, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium nitride, silicon carbide, zinc oxide, silicon oxycarbonitride, silicon, yittrium oxide, tantalum carbonitride, zirconium silicide, silicon carbonitride, zirconium aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide, silicon oxycarbide, or silicon oxide.

4. The semiconductor device of claim 2 , wherein the dielectric layer comprises silicon nitride.

5. The semiconductor device of claim 2 , wherein the dielectric layer is spaced apart from the APT implantation region by a first inner spacer layer.

6. The semiconductor device of claim 5 , wherein the first inner spacer layer comprises carbon-rich silicon carbonitride.

7. The semiconductor device of claim 6 ,

wherein each of plurality of inner spacer features comprises the first inner spacer layer and a second inner spacer layer,

wherein the second inner spacer layer comprises silicon.

8. The semiconductor device of claim 7 ,

wherein the second inner spacer layer of each of plurality of inner spacer features is spaced apart from the gate structure by the first inner spacer layer of each of plurality of inner spacer features.

9. The semiconductor device of claim 1 , wherein a top surface of the bottom dielectric feature is higher than a top surface of the APT implantation region.

10. The semiconductor device of claim 1 , wherein a top surface of the bottom dielectric feature is higher than a top surface of a bottommost one of the plurality of nanostructures.

11. A semiconductor structure, comprising:

an active region comprising a first channel region, a second channel region, and a source/drain region disposed between the first channel region and the second channel region;

a first plurality of nanostructures over the first channel region;

a second plurality of nanostructures over the second channel region;

a source/drain feature disposed between the first plurality of nanostructures and the second plurality of nanostructures;

a bottom dielectric feature disposed between the source/drain feature and the source/drain region; and

a germanium layer sandwiched between the bottom dielectric feature and the source/drain region,

wherein the bottom dielectric feature comprises silicon germanium oxide.

12. The semiconductor structure of claim 11 , further comprising:

a first plurality of inner spacer features interleaving the first plurality of nanostructures; and

a second plurality of inner spacer features interleaving the second plurality of nanostructures.

13. The semiconductor structure of claim 12 , further comprising:

a first dielectric layer disposed between the bottom dielectric feature and a bottommost one of the first plurality of inner spacer features; and

a second dielectric layer disposed between the bottom dielectric feature and a bottommost one of the second plurality of inner spacer features.

14. The semiconductor structure of claim 13 , wherein the source/drain feature is disposed on top surfaces of the bottom dielectric feature, the first dielectric layer, and the second dielectric layer.

15. The semiconductor structure of claim 13 , wherein the germanium layer does not extend between the first dielectric layer and the source/drain region as well as between the second dielectric layer and the source/drain region.

16. The semiconductor structure of claim 13 , wherein the first dielectric layer is spaced apart from the active region by an inner spacer layer.

17. The semiconductor structure of claim 16 , wherein the inner spacer layer comprises carbon-rich silicon carbonitride.

18. A structure, comprising:

an active region comprising a channel region and a source/drain region adjacent the channel region;

a plurality of nanostructures over the channel region, the plurality of nanostructure extending along a direction;

a bottom dielectric feature over the source/drain region; and

a dielectric layer disposed between the bottom dielectric feature and a bottommost nanostructure of the plurality of nanostructures along the direction,

wherein the bottom dielectric feature comprises silicon germanium oxide,

wherein the dielectric layer comprises silicon nitride.

19. The structure of claim 18 , further comprising:

an anti-punch-through (APT) implantation region over the channel region,

wherein the bottom dielectric feature is spaced apart from the APT implantation region by the dielectric layer.

20. The structure of claim 18 , further comprising:

a germanium layer sandwiched between the bottom dielectric feature and the source/drain region.