Memory device
A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.
1. A memory device comprising:
N memory layers;
a driver circuit layer;
a plurality of first wirings; and
a plurality of second wirings,
wherein N is a natural number greater than or equal to 2,
wherein the N memory layers are stacked over the driver circuit layer,
wherein the driver circuit layer comprises a plurality of first circuits,
wherein the plurality of first wirings extend in a stacking direction of the N memory layers and are arranged in a matrix of P rows and R columns and P and R are each a natural number greater than or equal to 1,
wherein the plurality of second wirings extend in the stacking direction and are arranged in a matrix of P rows and Q columns and Q is a natural number greater than or equal to 2,
wherein the N memory layers each comprise:
a plurality of memory cells arranged in a matrix of P rows and Q columns;
third wirings in Q columns;
fourth wirings in Q columns; and
fifth wirings in Q columns,
wherein in the memory layer in a k-th layer:
a memory cell in an i-th row and a 2×s−1-th column and a memory cell in the i-th row and a 2×s-th column are electrically connected to a first wiring in the i-th row and an s-th column, and
the memory cell in the i-th row and the 2×s−1-th column is electrically connected to a second wiring in the i-th row and the 2×s−1-th column, a third wiring in the 2×s−1-th column, a fourth wiring in the 2×s−1-th column, and a fifth wiring in the 2×s−1-th column,
wherein the memory cell in the i-th row and the 2×s−1-th column comprises a first transistor, a second transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein the one of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein the other electrode of the capacitor is electrically connected to the fifth wiring, and
wherein the first wiring and the second wiring are electrically connected to any one of the plurality of first circuits.
2. The memory device according to claim 1 further comprising a functional layer between the driver circuit layer and the plurality of memory cells.
3. The memory device according to claim 2 ,
wherein the functional layer comprises a plurality of second circuits, and
wherein the first wiring and the second wiring are electrically connected to the first circuit through any one of the plurality of second circuits.
4. The memory device according to claim 1 , wherein at least one of the first transistor and the second transistor comprises an oxide as a semiconductor.
5. The memory device according to claim 4 , wherein the oxide comprises one or both of In and Zn.
6. The memory device according to claim 4 , wherein the oxide comprises In, Ga, and Zn.
7. The memory device according to claim 1 , wherein one of the plurality of first circuits comprises a plurality of transistors, and the transistors each comprise silicon as a semiconductor.
8. The memory device according to claim 2 , wherein one of the plurality of first circuits comprises a plurality of transistors, and the transistors each comprise silicon as a semiconductor.
9. The memory device according to claim 3 , wherein one of the plurality of first circuits comprises a plurality of transistors, and the transistors each comprise silicon as a semiconductor.
10. The memory device according to claim 4 , wherein one of the plurality of first circuits comprises a plurality of transistors, and the transistors each comprise silicon as a semiconductor.
11. The memory device according to claim 5 , wherein one of the plurality of first circuits comprises a plurality of transistors, and the transistors each comprise silicon as a semiconductor.
12. The memory device according to claim 6 , wherein one of the plurality of first circuits comprises a plurality of transistors, and the transistors each comprise silicon as a semiconductor.