IP Library Granted Patent US 12,069,963
Granted Patent B2
US 12,069,963 · App. 17/461,243 · Granted Aug 20, 2024

Magnetic random access memory device and formation method thereof

Inventors: Harry-Hak-Lay Chuang (Hsinchu County, TW); Sheng-Chang Chen (Hsinchu County, TW); Hung Cho Wang (Taipei, TW); Sheng-Huang Huang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10N50/80H10B61/00H10N50/01H10N50/85
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Quick Facts
Patent No.
US 12,069,963
App. No.
17/461,243
Granted
Aug 20, 2024
Kind
B2
Abstract

A MRAM device includes a substrate, a first bottom electrode, a first MTJ stack, a first spacer, a topography-smoothing layer and a second ILD layer. The substrate includes a first ILD layer having a metal line. The first MTJ stack is over the first bottom electrode. The first spacer surrounds sidewalls of the first MTJ stack. The topography-smoothing layer extends over a top surface of the first ILD layer, along sidewalls of the first bottom electrode the first spacer. The topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer. The first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion. The second ILD layer is over the topography-smoothing layer and has a material different from a material of the topography-smoothing layer.

Claims (53)

1. A magnetic random access memory (MRAM) device, comprising:

a substrate comprising a first inter-layer dielectric (ILD) layer having a metal line;

a first bottom electrode over the metal line;

a first MTJ stack over the first bottom electrode, comprising:

a pinned layer;

a tunnel barrier layer over the pinned layer; and

a free layer over the tunnel barrier layer;

a first spacer surrounding sidewalls of the first MTJ stack;

a topography-smoothing layer extending over a top surface of the first ILD layer, along a sidewall of the first bottom electrode and along a sidewall of the first spacer, wherein the topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer, and the first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion; and

a second inter-layer dielectric (ILD) layer over the topography-smoothing layer, wherein the second ILD layer has a material different from a material of the topography-smoothing layer.

2. The device of claim 1 , wherein the topography-smoothing layer has a recessed region, and the second ILD layer has a portion embedded in the recessed region.

3. The device of claim 2 , wherein the portion of the second ILD layer has a width decreasing in a direction toward the substrate.

4. The device of claim 2 , wherein the topography-smoothing layer is in contact with the first spacer and the second ILD layer.

5. The device of claim 2 , wherein the topography-smoothing layer has a bottom portion under the first side portion, the bottom portion has a maximal vertical thickness greater than the maximal vertical thickness of the top portion.

6. The device of claim 5 , further comprising:

a second bottom electrode beside the first bottom electrode;

a second MTJ stack beside the first MTJ stack and over the second bottom electrode; and

a second spacer surrounding sidewalls of the second MTJ stack, wherein the topography-smoothing layer has a second side portion laterally surrounding the second spacer, and the second side portion, the bottom portion and the first side portion in combination form a U-shaped cross-section.

7. The device of claim 6 , wherein the first bottom electrode and the second bottom electrode have a spacing along a horizontal direction, and a ratio of the maximal lateral thickness of the first side portion to the spacing equals to about 0.01 to about 1.

8. The device of claim 1 , wherein the second ILD layer and the topography-smoothing layer have a bottommost interface at an elevation higher than a top surface of the first bottom electrode.

9. The device of claim 1 , further comprising:

a top electrode over the first MTJ stack; and

an upper metallization pattern formed within the second ILD layer, wherein the upper metallization pattern is over the top electrode and has a bottom surface in contact with the first spacer.

10. A magnetic random access memory (MRAM) device, comprising:

a substrate comprising a first inter-layer dielectric (ILD) layer having a first metal line, the substrate having a memory region and a logic region beside the memory region;

a bottom electrode over the first metal line;

a MTJ stack over the bottom electrode, comprising:

a pinned layer;

a tunnel barrier layer over the pinned layer; and

a free layer over the tunnel barrier layer;

a spacer surrounding sidewalls of the MTJ stack;

a topography-smoothing layer surrounding the MTJ stack, wherein the topography-smoothing layer is absent from the logic region; and

a second inter-layer dielectric (ILD) layer over the first ILD layer, wherein the second ILD layer has a first portion over the memory region and a second portion over the logic region, the first portion has a bottommost surface at an elevation higher than a bottommost surface of the second portion.

11. The device of claim 10 , wherein the topography-smoothing layer is in contact with the spacer and the bottom electrode.

12. The device of claim 10 , wherein the topography-smoothing layer has a width along a horizontal direction, and the width decreases in a direction away from the substrate.

13. The device of claim 10 , further comprising:

an etch stop layer on the memory region and the logic region of the substrate, wherein the substrate and the topography-smoothing layer are spaced apart by the etch stop layer.

14. The device of claim 10 , wherein the topography-smoothing layer is in contact with the first portion of the second ILD layer.

15. The device of claim 10 , further comprising:

a top electrode over the MTJ stack; and

a second metal line over the top electrode, wherein the second metal line is in contact with the topography-smoothing layer.

16. The device of claim 15 , wherein the topography-smoothing layer has a top surface higher than a bottom surface of the second metal line.

17. A method of forming a magnetic random access memory (MRAM) device, the method comprising:

forming a dielectric layer over a substrate comprising an inter-layer dielectric (ILD) layer having a metal line therein, wherein the substrate includes a memory region and a logic region beside the memory region;

forming a bottom electrode over the dielectric layer;

forming a magnetic tunnel junction (MTJ) stack over the bottom electrode;

forming a topography-smoothing material covering the MTJ stack and covering the dielectric layer on the logic region;

removing a first portion of the topography-smoothing material on the logic region to expose the dielectric layer while a second portion of the topography-smoothing material remains on the memory region; and

forming a second ILD layer over the second portion of the topography-smoothing material.

18. The method of claim 17 , further comprising:

before removing the first portion of the topography-smoothing material, thinning the topography-smoothing material.

19. The method of claim 18 , wherein thinning the topography-smoothing material is performed such that the topography-smoothing material has a vertical thickness less than a lateral thickness.

20. The device of claim 10 , wherein the topography-smoothing layer has opposite curved sidewalls on opposite sides of the MTJ stack, respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2021
From: CHUANG, HARRY-HAK-LAY; CHEN, SHENG-CHANG; WANG, HUNG CHO; HUANG, SHENG-HUANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 057330/0544 →
Continuity (1)
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