Temperature protection circuit
A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.
1. A circuit, comprising:
a temperature-sensitive voltage divider, comprising:
a temperature-sensitive resistor; and
a second resistor;
a first inverter commonly coupled to the temperature-sensitive resistor and the second resistor at a first node, wherein:
a temperature signal is generated at the first node, and
the first inverter comprises:
a first transistor having a gate to which the temperature signal is applied; and
a third resistor coupled to a first source/drain of the first transistor at a second node, wherein a control signal is output from the first inverter at the second node.
2. The circuit of claim 1 , comprising
a second inverter coupled to the second node, wherein the second inverter comprises:
a second transistor having a gate to which the control signal is applied; and
a fourth resistor coupled to a first source/drain of the second transistor at a third node, wherein a detection signal is output from the second inverter at the third node.
3. The circuit of claim 2 , comprising:
enable logic coupled between the third node and a load.
4. The circuit of claim 1 , comprising:
a second transistor, wherein a gate of the second transistor is coupled to second node.
5. The circuit of claim 4 , wherein:
a first terminal of the second resistor is coupled to the temperature-sensitive resistor, and
a second terminal of the second resistor is coupled to a first source/drain of the second transistor.
6. The circuit of claim 5 , comprising:
a fourth resistor, wherein:
a first terminal of the fourth resistor is coupled to the first source/drain of the second transistor, and
a second terminal of the fourth resistor is coupled to a second source/drain of the second transistor.
7. The circuit of claim 1 , wherein the second resistor is a temperature-insensitive resistor.
8. The circuit of claim 4 , wherein the gate of the second transistor is directly coupled to second node.
9. A circuit, comprising:
a temperature-sensitive resistor; and
detection logic comprising:
a first transistor having a gate coupled to a first terminal of the temperature-sensitive resistor; and
a second transistor having a first source/drain coupled to a first source/drain of the first transistor and a second source/drain coupled to a second terminal of the temperature-sensitive resistor.
10. The circuit of claim 9 , comprising:
a second resistor coupled to the first terminal of the temperature-sensitive resistor.
11. The circuit of claim 10 , wherein a first terminal of the second resistor, the first terminal of the temperature-sensitive resistor, and the gate of the first transistor are commonly coupled.
12. The circuit of claim 10 , comprising:
a third transistor, wherein:
a first source/drain of the third transistor is coupled to a second source/drain of the second transistor, and
a second source/drain of the third transistor is coupled to a second terminal of the second resistor.
13. The circuit of claim 10 , wherein the second resistor is a temperature-insensitive resistor.
14. The circuit of claim 9 , wherein the second terminal of the temperature-sensitive resistor is coupled to ground.
15. The circuit of claim 9 , wherein the detection logic comprises a third transistor having a first source/drain coupled to the first source/drain of the first transistor and a gate coupled to a reference voltage source.
16. A circuit, comprising:
a temperature-sensitive voltage divider, comprising:
a temperature-sensitive resistor; and
a second resistor;
a first inverter having an input terminal coupled to a first terminal of the temperature-sensitive resistor; and
a shunting transistor having a gate coupled to an output terminal of the first inverter and a first source/drain coupled to a first terminal of the second resistor.
17. The circuit of claim 16 , comprising a second inverter having an input terminal coupled to the output terminal of the first inverter.
18. The circuit of claim 16 , wherein the shunting transistor has a second source/drain coupled to a second terminal of the second resistor.
19. The circuit of claim 16 , wherein the shunting transistor has a body coupled to a second terminal of the second resistor.
20. The circuit of claim 16 , wherein the second resistor is a temperature-insensitive resistor.