IP Library › Granted Patent US 12,080,652
Granted Patent B2
US 12,080,652 · App. 18/216,102 · Granted Sep 3, 2024

Microelectronic assemblies with communication networks

Inventors: Adel A. Elsherbini (Tempe, AZ); Amr Elshazly (Hillsboro, OR); Arun Chandrasekhar (Chandler, AZ); Shawna M. Liff (Scottsdale, AZ); Johanna M. Swan (Scottsdale, AZ)
Assignee: Intel Corporation
H01L23/5385H01L24/16H01L24/17H01L25/00H01L2224/16225H01L2224/1703
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Quick Facts
Patent No.
US 12,080,652
App. No.
18/216,102
Granted
Sep 3, 2024
Kind
B2
Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Claims (53)

1. A microelectronic assembly, comprising:

a package substrate;

a first die, a second die, a third die and a fourth die in a first plane above the package substrate;

a fifth die in a second plane above the first plane, the fifth die having a first side and a second side laterally opposite the first side, the fifth die vertically overlapping the first die and the second die at the first side, and the fifth die vertically overlapping the third die and the fourth die at the second side;

a sixth die in the second plane, the sixth die vertically overlapping with the first die, the sixth die at the first side of the fifth die;

a seventh die in the second plane, the seventh die vertically overlapping with the second die, the seventh die at the first side of the fifth die;

an eighth die in the second plane, the eighth die vertically overlapping with the third die, the eighth die at the second side of the fifth die;

a ninth die in the second plane, the ninth die vertically overlapping with the fourth die, the ninth die at the second side of the fifth die;

a first interconnect vertically between the fifth die and the package substrate, the first interconnect laterally between the first die and the third die; and

a second interconnect vertically between the eighth die and the package substrate, the second interconnect laterally spaced apart from the third die.

2. The microelectronic assembly of claim 1 , further comprising:

a third interconnect vertically between the fifth die and the package substrate, the third interconnect laterally between the first die and the fourth die.

3. The microelectronic assembly of claim 1 , further comprising:

a third interconnect vertically between the ninth die and the package substrate, the third interconnect laterally spaced apart from the fourth die.

4. The microelectronic assembly of claim 1 , further comprising:

a third interconnect vertically between the fifth die and the package substrate, the third interconnect laterally between the first die and the fourth die; and

a fourth interconnect vertically between the ninth die and the package substrate, the fourth interconnect laterally spaced apart from the fourth die.

5. The microelectronic assembly of claim 1 , wherein the first die, the second die, the third die and the fourth die vertically overlap with a corresponding corner of the fifth die.

6. The microelectronic assembly of claim 1 , wherein the first interconnect and the second interconnect are in the first plane.

7. The microelectronic assembly of claim 1 , wherein the first interconnect and the second interconnect have a vertical height greater than a vertical height of each of the first die, the second die, the third die and the fourth die.

8. The microelectronic assembly of claim 1 , wherein the first interconnect extends from the fifth die to the package substrate.

9. The microelectronic assembly of claim 1 , wherein the second interconnect extends from the eighth die to the package substrate.

10. A microelectronic assembly, comprising:

a package substrate;

a first die, a second die, a third die and a fourth die at a first height above the package substrate;

a fifth die at a second height above the package substrate, the second height above the first height, the fifth die having a first side and a second side laterally opposite the first side, the fifth die vertically overlapping the first die and the second die at the first side, and the fifth die vertically overlapping the third die and the fourth die at the second side;

a sixth die at the second height above the package substrate, the sixth die vertically overlapping with the first die, the sixth die laterally spaced apart from the first side of the fifth die;

a seventh die at the second height above the package substrate, the seventh die vertically overlapping with the second die, the seventh die at the first side of the fifth die;

an eighth die at the second height above the package substrate, the eighth die vertically overlapping with the third die, the eighth die laterally spaced apart from the second side of the fifth die;

a ninth die at the second height above the package substrate, the ninth die vertically overlapping with the fourth die, the ninth die at the second side of the fifth die;

a first interconnect vertically between the fifth die and the package substrate, the first interconnect laterally between the first die and the third die; and

a second interconnect vertically between the eighth die and the package substrate, the second interconnect laterally spaced apart from the third die.

11. The microelectronic assembly of claim 10 , further comprising:

a third interconnect vertically between the fifth die and the package substrate, the third interconnect laterally between the first die and the fourth die.

12. The microelectronic assembly of claim 10 , further comprising:

a third interconnect vertically between the ninth die and the package substrate, the third interconnect laterally spaced apart from the fourth die.

13. The microelectronic assembly of claim 10 , further comprising:

a third interconnect vertically between the fifth die and the package substrate, the third interconnect laterally between the first die and the fourth die; and

a fourth interconnect vertically between the ninth die and the package substrate, the fourth interconnect laterally spaced apart from the fourth die.

14. The microelectronic assembly of claim 10 , wherein the first die, the second die, the third die and the fourth die vertically overlap with a corresponding corner of the fifth die.

15. The microelectronic assembly of claim 10 , wherein the first interconnect and the second interconnect are at the first height.

16. The microelectronic assembly of claim 10 , wherein the first interconnect and the second interconnect have a vertical height greater than a vertical height of each of the first die, the second die, the third die and the fourth die.

17. The microelectronic assembly of claim 10 , wherein the first interconnect extends from the fifth die to the package substrate, and wherein the second interconnect extends from the eighth die to the package substrate.

18. A microelectronic assembly, comprising:

a package substrate;

a first die and a second die in a first plane above the package substrate;

a third die in a second plane above the first plane, the third die having a first side and a second side laterally opposite the first side, the third die vertically overlapping the first die at the first side, and the third die vertically overlapping the second die at the second side;

a fourth die in the second plane, the fourth die vertically overlapping with the first die, the fourth die at the first side of the third die;

a fifth die in the second plane, the fifth die vertically overlapping with the second die, the fifth die at the second side of the third die;

a first interconnect vertically between the third die and the package substrate, the first interconnect laterally between the first die and the third die; and

a second interconnect vertically between the fifth die and the package substrate, the second interconnect laterally spaced apart from the second die.

19. The microelectronic assembly of claim 18 , wherein the first interconnect and the second interconnect have a vertical height greater than a vertical height of each of the first die and the second die.

20. The microelectronic assembly of claim 18 , wherein the first interconnect extends from the third die to the package substrate, and wherein the second interconnect extends from the fifth die to the package substrate.

Continuity (3)
Continuation 17514528 · Oct 29, 2021
Continuation 16648432
Related Publication 20230343716A1 · Oct 26, 2023
Cited By (2)
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