Vector computational unit
A microprocessor system comprises a computational array and a vector computational unit. The computational array includes a plurality of computation units. The vector computational unit is in communication with the computational array and includes a plurality of processing elements. The processing elements are configured to receive output data elements from the computational array and process in parallel the received output data elements.
1. A microprocessor system, comprising:
a computational array that includes a plurality of computation units, wherein the computation units are grouped into a plurality of lanes; and
a vector computational unit in communication with the computational array, the vector computational unit comprising a plurality of processing elements, wherein each processing element is connected to a corresponding computation unit in a last row of the plurality of computation units, wherein the vector computational unit is configured to process information received as output from the lanes to form a processing result, wherein each lane outputs a plurality of output portions which form the information,
wherein the vector computational unit includes a plurality of registers, wherein each register receives output from the plurality of lanes, and wherein each register is configured to be aliased to select a same subset of each of the pluralities of output portions received from each lane.
2. The system of claim 1 , wherein each lane comprises a first-in-first out (FIFO) queue.
3. The system of claim 2 , wherein each lane comprises a subset of the computation units arranged as a vector.
4. The system of claim 1 , wherein the registers are associated with a particular bit-size.
5. The system of claim 4 , wherein the particular bit-size of a first register of the plurality of registers is based on at least one of:
an operation type;
a data type of the corresponding output portions; or
a load instruction.
6. The system of claim 1 , wherein aliasing determines an alignment of the same subset of each of the pluralities of output portions as loaded in the registers.
7. The system of claim 6 , wherein an operand for operations performed by each of the plurality of processing elements is based on the aliasing.
8. The system of claim 1 , wherein selecting output portions comprises selecting byte, half-word, or word output.
9. The system of claim 1 , wherein aliasing is performed based on use of a bit mask.
10. The system of claim 1 , wherein:
a first register of the plurality of registers is aliased to operate on a first subset of corresponding output portions from each of the plurality of lanes; and
a second register of the plurality of registers is aliased to operate on a second subset of corresponding output portions from each of the plurality of lanes.
11. The system of claim 10 , wherein the first subset is the same as the second subset.
12. A method implemented by a microprocessor system, the method comprising:
receiving a single processor instruction for a vector computational unit, wherein the vector computational unit is in communication with a computational array and includes a plurality of processing elements;
receiving information from the computational array, wherein the computational array includes a plurality of computation units grouped into a plurality of lanes, and wherein each lane outputs a plurality of output portions which form the received information and
processing the information in parallel to form a processing result, wherein the vector computational unit includes a plurality of registers, wherein each register receives output from the plurality of lanes, and wherein each register is configured to be aliased to select a same subset of each of the pluralities of output portions received from each lane.
13. The method of claim 12 , wherein each lane comprises a first-in-first out (FIFO) queue.
14. The method of claim 13 , wherein each lane comprises a subset of the computation units arranged as a vector.
15. The method of claim 12 , wherein the registers are associated with a particular bit-size.
16. The method of claim 15 , wherein the particular bit-size of a first register of the plurality of registers is based on at least one of:
an operation type;
a data type of the output portions; or
a load instruction.
17. The method of claim 12 , wherein aliasing determines an alignment of the same subset of each of the pluralities of output portions as loaded in the registers.
18. The method of claim 12 , wherein selecting output portions comprises selecting byte, half-word, or word output.
19. The method of claim 12 , wherein aliasing is performed based on use of a bit mask.
20. The method of claim 12 , wherein:
a first register of the plurality of registers is aliased to operate on a first subset of corresponding output portions from each of the plurality of lanes; and
a second register of the plurality of registers is aliased to operate on a second subset of corresponding output portions from each of the plurality of lanes.
21. The method of claim 20 , wherein the first subset is the same as the second subset.