IP Library Granted Patent US 12,092,671
Granted Patent B2
US 12,092,671 · App. 17/794,044 · Granted Sep 17, 2024

Capacitance measurement apparatus

Inventor: Chen Chen (Beijing, CN)
Assignee: CHIPONE TECHNOLOGY (BEIJING) CO., LTD.
G01R27/2605G01D5/24
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Quick Facts
Patent No.
US 12,092,671
App. No.
17/794,044
Granted
Sep 17, 2024
Kind
B2
Abstract

Provided is a capacitance measurement apparatus ( 200 ), including: a channel capacitor ( 101 ) configured to generate different capacitance values according to a sensing signal; a measurement circuit ( 220 ) connected to the channel capacitor ( 101 ) and configured to access a pulse signal and measure a capacitance value of the channel capacitor ( 101 ); and an adjustment circuit ( 210 ) connected between the channel capacitor ( 101 ) and the measurement circuit ( 220 ), and configured to cancel a basic capacitance value of the channel capacitor ( 101 ) and generate a varying capacitance value of the channel capacitor ( 101 ). The measurement circuit ( 220 ) is further configured to convert the varying capacitance value of the channel capacitor ( 101 ) into an output signal. A reference capacitance of the channel capacitor ( 101 ) is canceled by means of the adjustment circuit ( 210 ), thereby increasing the valid range of an output signal of the measurement circuit ( 220 ).

Claims (52)

1. A capacitance detection apparatus, comprising:

a channel capacitor, configured to generate different capacitance values according to a sensing signal;

a detection circuit, connected to the channel capacitor, and configured to access a pulse signal, and detect a capacitance value of the channel capacitor; and

an adjustment circuit, connected between the channel capacitor and the detection circuit, and configured to cancel out a basic capacitance value of the channel capacitor, and generate a varying capacitance value of the channel capacitor,

wherein the detection circuit is further configured to convert the varying capacitance value of the channel capacitor into an output signal;

the apparatus further comprising:

a first reset switch, wherein the first reset switch has a first end connected to a forward input end of the detection circuit, and a second end connected to a reverse input end of the detection circuit.

2. The apparatus according to claim 1 , wherein the adjustment circuit comprises:

a reduced-basis element; and

a first reduced-basis switch, wherein the first reduced-basis switch has one end connected to the reduced-basis element, and the other end connected to a positive pole of the channel capacitor, and when the first reduced-basis switch is closed, the channel capacitor is charged or discharged by the reduced-basis element.

3. The apparatus according to claim 1 , wherein the detection circuit comprises:

an operational amplifier, wherein a reverse input end of the operational amplifier is connected to the positive pole of the channel capacitor, and a forward input end of the operational amplifier is connected to a pulse signal port; and

a feedback capacitor, connected between the reverse input end of the operational amplifier and an output end of the operational amplifier,

wherein the detection circuit is configured to detect the varying capacitance value of the channel capacitor when the operational amplifier accesses a pulse signal through the pulse signal port.

4. The apparatus according to claim 1 , further comprising:

a detection switch, wherein the detection switch is connected between the second end of the first reset switch and the reverse input end of the detection circuit.

5. The apparatus according to claim 4 , wherein the adjustment circuit comprises:

a reduced-basis element; and

a first reduced-basis switch, wherein the first reduced-basis switch has one end connected to the reduced-basis element, and the other end connected to a positive pole of the channel capacitor, and when the first reduced-basis switch is closed, the channel capacitor is charged or discharged by the reduced-basis element.

6. The apparatus according to claim 4 , wherein the detection circuit comprises:

an operational amplifier, wherein a reverse input end of the operational amplifier is connected to the positive pole of the channel capacitor, and a forward input end of the operational amplifier is connected to a pulse signal port; and

a feedback capacitor, connected between the reverse input end of the operational amplifier and an output end of the operational amplifier,

wherein the detection circuit is configured to detect the varying capacitance value of the channel capacitor when the operational amplifier accesses a pulse signal through the pulse signal port.

7. The apparatus according to claim 1 , wherein the detection circuit comprises:

an operational amplifier, wherein a reverse input end of the operational amplifier is connected to the positive pole of the channel capacitor, and a forward input end of the operational amplifier is connected to a pulse signal port; and

a feedback capacitor, connected between the reverse input end of the operational amplifier and an output end of the operational amplifier,

wherein the detection circuit is configured to detect the varying capacitance value of the channel capacitor when the operational amplifier accesses a pulse signal through the pulse signal port.

8. The apparatus according to claim 7 , wherein the detection circuit comprises:

a second reset switch, wherein the second reset switch is connected in parallel to the feedback capacitor.

9. The apparatus according to claim 1 , wherein the adjustment circuit comprises:

a reduced-basis element; and

a first reduced-basis switch, wherein the first reduced-basis switch has one end connected to the reduced-basis element, and the other end connected to a positive pole of the channel capacitor, and when the first reduced-basis switch is closed, the channel capacitor is charged or discharged by the reduced-basis element.

10. The apparatus according to claim 9 , wherein the reduced-basis element is a current source; and the reduced-basis element comprises:

a first current source, wherein an input end of the first current source is connected to the first reduced-basis switch.

11. The apparatus according to claim 10 , wherein the reduced-basis element further comprises:

a second current source; and

a third reduced-basis switch, wherein the third reduced-basis switch has one end connected to the positive pole of the channel capacitor, and the other end connected to an output end of the second current source.

12. The apparatus according to claim 9 , wherein the reduced-basis element is a reduced-basis capacitor, a positive pole of the reduced-basis capacitor is connected to the first reduced-basis switch, and a negative pole of the reduced-basis capacitor is connected to a reference level port through a second reduced-basis switch.

13. The apparatus according to claim 12 , wherein the first reduced-basis switch and the second reduced-basis switch operate in a same timing sequence.

14. The apparatus according to claim 13 , wherein the adjustment circuit further comprises:

a first level switch, wherein the first level switch has one end connected to the positive pole of the reduced-basis capacitor, and the other end connected to a first level port.

15. The apparatus according to claim 12 , wherein the adjustment circuit further comprises:

a first level switch, wherein the first level switch has one end connected to the positive pole of the reduced-basis capacitor, and the other end connected to a first level port.

16. The apparatus according to claim 15 , wherein the first level switch comprises:

a first sub-switch, wherein the first sub-switch has one end connected to the positive pole of the reduced-basis capacitor, and the other end connected to a low level port of the first level port; and

a second sub-switch, wherein the second sub-switch has one end connected to the positive pole of the reduced-basis capacitor, and the other end connected to a high level port of the first level port.

17. The apparatus according to claim 16 , wherein the adjustment circuit further comprises:

a second level switch, wherein the second level switch has one end connected to the negative pole of the reduced-basis capacitor, and the other end connected to a second level port.

18. The apparatus according to claim 17 , wherein the second level switch comprises:

a third sub-switch, wherein the third sub-switch has one end connected to the negative pole of the reduced-basis capacitor, and the other end connected to a low level port of the second level port; and

a fourth sub-switch, wherein the fourth sub-switch has one end connected to the negative pole of the reduced-basis capacitor, and the other end connected to a high level port of the second level port.

19. The apparatus according to claim 18 , wherein the first sub-switch and the fourth sub-switch operate in a same timing sequence, and the second sub-switch and the third sub-switch operate in a same timing sequence.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2022
From: CHEN, CHEN
To: CHIPONE TECHNOLOGY (BEIJING) CO., LTD.
Reel/Frame 060564/0893 →
Priority Claims (1)
CN 202010167216.2 · Mar 11, 2020 · national
Continuity (1)
Related Publication 20230065600A1 · Mar 2, 2023