Forming low-resistance capping layer over metal gate electrode
A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
1. A method, comprising:
forming a gate structure that includes forming a high-k gate dielectric and a metal-containing gate electrode over a plurality of active region structures that each protrude upwards in a vertical direction, wherein the metal-containing gate electrode includes a plurality of conductive layers and a non-conductive layer, wherein the active region structures each extend in a first horizontal direction, and wherein the gate structure extends in a second horizontal direction different from the first horizontal direction;
etching back a portion of the gate structure;
growing a conductive capping layer directly on upper surfaces of the conductive layers but not directly on an upper surface of the non-conductive layer after the gate structure has been etched back; and
forming a gate via over the conductive capping layer, wherein in a cross-sectional view defined by the first horizontal direction and the vertical direction, the conductive capping layer is substantially wider than the gate via.
2. The method of claim 1 , wherein the growing the conductive capping layer is performed such that a bottom surface of the conductive capping layer is grown to have recesses corresponding to locations of the non-conductive layer.
3. The method of claim 1 , wherein the growing the conductive capping layer comprises growing the conductive capping layer over a substantial entirety of an upper surface of the etched gate structure in the second horizontal direction.
4. The method of claim 1 , wherein the growing the conductive capping layer comprises growing a metal layer with a lower resistivity than the gate via and the etched gate structure as the conductive capping layer.
5. The method of claim 1 , wherein after the conductive capping layer has been grown on the gate structure, the non-conductive layer has a greater vertical elevation than one of the conductive layers disposed directly adjacent to the non-conductive layer.
6. The method of claim 1 , wherein the growing the conductive capping layer comprises growing fluorine-free-tungsten (FFW) as the conductive capping layer.
7. The method of claim 1 , wherein the conductive capping layer is grown using a precursor that comprises: WC15, H2, WF6, or SiH4.
8. The method of claim 1 , wherein the conductive capping layer is grown using a selective growth process performed at a process temperature in a range between about 400 degrees Celsius and about 500 degrees Celsius, for a process duration between about 2 minutes and about 30 minutes, and at a process pressure in a range between about 2 Torr and about 500 Torr.
9. A method, comprising:
forming a gate structure over a plurality of active region structures that each protrude upwards in a vertical direction, wherein the active region structures each extend in a first horizontal direction, and wherein the gate structure extends in a second horizontal direction different from the first horizontal direction;
etching back a portion of the gate structure;
depositing a glue layer over the etched gate structure after the gate structure has been etched back, wherein the glue layer defines a recess;
filling the recess with a conductive capping layer;
performing a planarization process to the glue layer and the conductive capping layer; and
forming a gate via over the planarized conductive capping layer, wherein the conductive capping layer includes a metal layer having a lower resistivity than the gate via and the etched gate structure, and wherein in a cross-sectional view defined by the first horizontal direction and the vertical direction, the conductive capping layer is substantially wider than the gate via.
10. The method of claim 9 , wherein:
the forming the gate structure includes forming a high-k gate dielectric and a metal-containing gate electrode, the metal-containing gate electrode includes a plurality of conductive layers and a non-conductive layer; and
the depositing the glue layer comprises depositing the glue layer directly on upper surfaces of the conductive layers and the non-conductive layer.
11. The method of claim 9 , wherein the depositing the glue layer comprises depositing a titanium nitride layer as the glue layer.
12. The method of claim 9 , wherein the filling the recess is performed such that the conductive capping layer is formed over a substantial entirety of an upper surface of the etched gate structure in the second horizontal direction.
13. A method, comprising:
forming a gate structure at least in part by forming a high-k gate dielectric and forming a metal-containing gate electrode over the high-k gate dielectric, wherein the metal-containing gate electrode includes a plurality of metallic layers and a non-metallic layer;
etching a portion of the gate structure that is located over a plurality of active regions, the active regions each protruding upwards in a vertical direction in a cross-sectional side view, the gate structure partially wrapping around the active regions in the cross-sectional side view, wherein the active regions each extend in a first horizontal direction in a top view, and wherein the gate structure extends in a second horizontal direction different from the first horizontal direction in the top view;
forming a conductive layer over the etched gate structure after the gate structure has been etched, wherein a bottom surface of the conductive layer has recesses corresponding to locations of the non-metallic layer; and
forming a gate via over the conductive layer, wherein the conductive layer has a greater dimension in the first horizontal direction than the gate via in the top view.
14. The method of claim 13 , wherein the forming the conductive layer comprises selectively growing the conductive layer directly on upper surfaces of the metallic layers, but not directly on an upper surface of the non-metallic layer.
15. The method of claim 13 , wherein the forming the conductive layer comprises growing the conductive layer over a substantial entirety of an upper surface of the etched gate structure in the second horizontal direction.
16. The method of claim 13 , wherein the conductive layer has a lower resistivity than the gate via or the gate structure.
17. The method of claim 13 , wherein a dimension of the conductive layer in the first horizontal direction is at least multiple times greater than a dimension of the gate via in the first horizontal direction.
18. The method of claim 13 , wherein the forming the conductive layer comprises depositing a tungsten-containing material.
19. The method of claim 13 , further comprising forming a glue layer between the etched gate structure and the conductive layer.
20. The method of claim 13 , wherein the first horizontal direction is perpendicular to the second horizontal direction.