Method for predicting fluctuation of circuit path delay on basis of machine learning

1. A method for manufacturing an integrated circuit based on a prediction of a fluctuation of circuit path delay on the basis of machine learning, comprising the following steps:

S1: selecting suitable sample characteristics by means of analyzing a relationship between circuit characteristics and a path delay;

S2: generating a random path by means of enumerating values of randomized parameters, acquiring a maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3σ standard, and using the sample characteristics and the path delay of the reliable path as a sample set;

S3: establishing a path delay prediction model, and adjusting parameters of the path prediction model;

S4: verifying a precision and a stability of the path delay prediction model;

S5: obtaining an output path delay;

S6: generating a layout of the integrated circuit based on the output path delay; and

S7: manufacturing the integrated circuit based on the layout, wherein the path delay prediction model in step S3 is established by the following sub-steps:

S3.1: randomly selecting n samples in a returnable manner from data in a training set, and using the samples as the training set for generating a regression tree;

S3.2: generating an unpruned regression tree for each sample, and modifying the regression tree; and performing random sampling of prediction variables at each node of the unpruned regression tree, and selecting an optimum segmentation point from these prediction variables; and

S3.3: establishing the path delay prediction model by data clustering of n unpruned regression trees to predict a new path delay, and using an average value of clustering results as the output path delay by the path delay prediction model.

2. The method according to claim 1 , wherein the sample characteristics in step S1 comprise a stage of a circuit path, a type of each cell, a size of each cell, a polarity of each cell, a load capacitance of each cell and a path intrinsic delay.

3. The method according to claim 1 , wherein the adjusting the parameters of the model in step S3 comprises the following process: increasing the number of decision trees and the number of variables at each node, and selecting a parameter value in the case of a minimum error to optimize the model.

4. The method according to claim 1 , wherein step S4 comprises the following process: verifying the precision of the path delay prediction model by calculating an average error of a training set, an average error and a maximum absolute error of a test set; and verifying the stability of the path delay prediction model by changing the number of samples in the test set and observing a change in the average error of the test set.

5. The method according to claim 1 , wherein the generating the random path in step S2 comprises the following process: selecting and randomly setting circuit structure parameters and parasitic parameters of the path, and generating a SPICE netlist file corresponding to the random path, wherein the circuit structure parameters comprise a stage of a circuit path, a type of each cell and size of each cell, and a polarity of a path input signal; and the parasitic parameters comprise a load capacitance of each cell.