IP Library Granted Patent US 12,113,721
Granted Patent B2
US 12,113,721 · App. 18/205,856 · Granted Oct 8, 2024

Network interface and buffer control method thereof

Inventors: Nobuhiro Yokoi (Tokyo, JP); Hiroka Ihara (Tokyo, JP)
Assignee: HITACHI, LTD.
H04L49/9052H04L49/9084
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Quick Facts
Patent No.
US 12,113,721
App. No.
18/205,856
Granted
Oct 8, 2024
Kind
B2
Abstract

A network interface includes a processor, memory, and a cache between the processor and the memory. The processor secures a plurality of buffers for storing transfer data in the memory, and manages an allocation order of available buffers of the plurality of buffers. The processor returns a buffer released after data transfer to a position before a predetermined position of the allocation order.

Claims (36)

1. A network interface comprising:

a processor;

a memory; and

a cache between the processor and the memory,

wherein the processor is configured to:

secure a plurality of buffers for storing transfer data in the memory, and

determine whether or not a buffer is required to be allocated for new transfer data based on an amount of buffer in use, and

a maximum value of the number of buffers capable of being used simultaneously in the plurality of buffers is set,

wherein the processor is configured to allocate a plurality of buffer groups in the memory,

wherein each of the plurality of buffer groups is composed of a plurality of buffers of the same size,

wherein the plurality of buffer groups have different buffer sizes from each other, and

wherein when a transfer data size is equal to or less than a maximum buffer size of the different buffer sizes, the processor is configured to select a buffer group having a minimum buffer size among buffer sizes equal to or greater than the transfer data size to store the transfer data.

2. The network interface according to claim 1 ,

wherein the processor is configured to return a buffer released after data transfer to a head position of an allocation order of available buffers of the plurality of buffers.

3. The network interface according to claim 1 ,

wherein when the transfer data size is greater than the maximum buffer size, the processor is configured to secure a new buffer area equal to or greater than the transfer data size.

4. The network interface according to claim 1 ,

wherein when the transfer data size is greater than the maximum buffer size, the processor is configured to divide the transfer data and allocate a buffer selected from the plurality of buffer groups to the divided transfer data.

5. The network interface according to claim 1 ,

wherein a maximum value of the number of buffers capable of being used simultaneously in each of the plurality of buffer groups is set.

6. The network interface according to claim 1 ,

wherein the processor is configured to:

determine whether or not a buffer is required to be allocated for new transfer data based on an amount of buffer in use when the transfer data size is equal to or less than the maximum buffer size, and

skip the determination when the transfer data size is greater than the maximum buffer size.

7. The network interface according to claim 1 ,

wherein the processor is configured to:

manage an allocation order of available buffers of the plurality of buffers, and

return a buffer released after data transfer to a position before a predetermined position of the allocation order.

8. A buffer control method in a network interface including a processor, a memory, and a cache between the processor and the memory, the buffer control method comprising:

by the processor, securing a plurality of buffers for storing transfer data in the memory; and

by the processor, determining whether or not a buffer is required to be allocated for new transfer data based on an amount of buffer in use,

wherein a maximum value of the number of buffers capable of being used simultaneously in the plurality of buffers is set,

wherein the method further comprises, by the processor, allocating a plurality of buffer groups in the memory,

wherein each of the plurality of buffer groups is composed of a plurality of buffers of the same size,

wherein the plurality of buffer groups have different buffer sizes from each other, and

wherein when a transfer data size is equal to or less than a maximum buffer size of the different buffer sizes, the processor is configured to select a buffer group having a minimum buffer size among buffer sizes equal to or greater than the transfer data size to store the transfer data.

Assignments (1)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
Priority Claims (1)
JP 2022-048675 · Mar 24, 2022 · national
Continuity (2)
Continuation 17896204 · Aug 26, 2022
Related Publication 20230328008A1 · Oct 12, 2023
Cited By (1)
US 12,375,431