IP Library Granted Patent US 12,141,439
Granted Patent B2
US 12,141,439 · App. 17/821,894 · Granted Nov 12, 2024

Memory command assignment based on command processor workload

Inventors: Guang Shen (Shanghai, CN); Yue Wei (Shanghai, CN)
Assignee: Micron Technology, Inc.
G06F3/0613G06F3/0635G06F3/0679
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Quick Facts
Patent No.
US 12,141,439
App. No.
17/821,894
Granted
Nov 12, 2024
Kind
B2
Abstract

Implementations described herein relate to memory command assignment based on command processor workload. In some implementations, a memory device may determine a first command type of a first memory command. The memory device may identify a first command processor, associated with the first command type, that is one of multiple command processors configured to execute memory commands. The first command processor may be configured to execute only commands having the first command type unless a computational credit condition, associated with another command processor, is satisfied. The memory device may determine that a cumulative computational credit value associated with the first command processor does not satisfy a condition. The memory device may assign the first memory command to the first command processor for execution based on determining that the cumulative computational credit value associated with the first command processor does not satisfy the condition.

Claims (73)

1. A memory device, comprising:

one or more components configured to:

detect a memory command to be executed;

determine a command type of the memory command,

wherein the command type is one of a first command type or a second command type;

identify a primary command processor associated with the command type,

wherein the primary command processor is one of a plurality of command processors that are configured to execute memory commands for the memory device, and

wherein the primary command processor is configured to execute only commands having the first command type unless a first computational credit condition, associated with another command processor of the plurality of command processors, is satisfied;

determine a cumulative computational credit value, associated with the primary command processor, based on memory commands that are assigned to the primary command processor; and

selectively assign the memory command to the primary command processor or a secondary command processor, of the plurality of command processors, based on whether the cumulative computational credit value satisfies a threshold,

wherein the secondary command processor is configured to execute only commands having the second command type unless a second computational credit condition, associated with another command processor of the plurality of command processors, is satisfied.

2. The memory device of claim 1 , wherein the cumulative computational credit value associated with the primary command processor is based on all computational credit values corresponding to all memory commands that are assigned to the primary command processor for execution.

3. The memory device of claim 1 , wherein the one or more components, to selectively assign the memory command to the primary command processor or the secondary command processor, are configured to:

assign the memory command to the primary command processor based on a determination that the cumulative computational credit value does not satisfy the threshold; and

wherein the one or more components are further configured to:

modify the cumulative computational credit value associated with the primary command processor based on assigning the memory command to the primary command processor and based on a computational credit value associated with the memory command.

4. The memory device of claim 3 , wherein the computational credit value associated with the memory command is based on at least one of:

the command type of the memory command, or

a data transfer size indicated in the memory command.

5. The memory device of claim 3 , wherein the memory command is a first memory command; and

wherein the one or more components are further configured to:

detect a second memory command to be executed, wherein the second memory command is a same command type as the first memory command;

determine a current cumulative computational credit value, associated with the primary command processor, based on modifying the cumulative computational credit value; and

selectively assign the second memory command to the primary command processor or the secondary command processor based on whether the current cumulative computational credit value satisfies the threshold.

6. The memory device of claim 1 , wherein the cumulative computational credit value is a first cumulative computational credit value;

wherein the one or more components, to selectively assign the memory command to the primary command processor or the secondary command processor, are configured to:

assign the memory command to the secondary command processor based on a determination that the first cumulative computational credit value satisfies the threshold; and

wherein the one or more components are further configured to:

modify a second cumulative computational credit value associated with the secondary command processor based on assigning the memory command to the secondary command processor and based on a computational credit value associated with the memory command.

7. The memory device of claim 6 , wherein the second computational credit condition is that the first cumulative computational credit value satisfies the threshold.

8. The memory device of claim 1 , wherein the first computational credit condition is that another cumulative computational credit value, associated with a command processor other than the primary command processor, satisfies the threshold.

9. The memory device of claim 1 , wherein the first command type is associated with a first computational credit value and the second command type is associated with a second computational credit value that is different from the first computational credit value.

10. The memory device of claim 1 , wherein the first command type is one of a read command type or a write command type, and

wherein the second command type is the other of the read command type or the write command type.

11. The memory device of claim 10 , wherein the write command type is associated with a computational credit value that is greater in magnitude than a computational credit value associated with the read command type.

12. A method, comprising:

determining, by a memory device and from one of a first command type or a second command type, a command type of a memory command to be executed;

identifying, by the memory device, a primary command processor, associated with the command type, from a plurality of command processors configured to execute memory commands for the memory device,

wherein the primary command processor is configured to execute only commands having the first command type unless a first computational credit condition, associated with another command processor of the plurality of command processors, is satisfied;

determining, by the memory device, a cumulative computational credit value, associated with the primary command processor, based on memory commands that are assigned to the primary command processor; and

assigning the memory command to the primary command processor or a secondary command processor, of the plurality of command processors, based on whether the cumulative computational credit value satisfies a threshold,

wherein the secondary command processor is configured to execute only commands having the second command type unless a second computational credit condition, associated with another command processor of the plurality of command processors, is satisfied.

13. The method of claim 12 , wherein the cumulative computational credit value is based on computational credit values corresponding to all memory commands assigned to the primary command processor.

14. The method of claim 12 , wherein assigning the memory command to the primary command processor or the secondary command processor comprises:

assigning the memory command to the primary command processor based on the cumulative computational credit value not satisfying the threshold.

15. The method of claim 14 , further comprising:

modifying the cumulative computational credit value associated with the primary command processor based on assigning the memory command to the primary command processor.

16. The method of claim 12 , wherein assigning the memory command to the primary command processor or the secondary command processor comprises:

assigning the memory command to the secondary command processor based on the cumulative computational credit value satisfying the threshold.

17. The method of claim 16 , further comprising:

modifying a second cumulative computational credit value associated with the secondary command processor based on assigning the memory command to the secondary command processor.

18. The method of claim 12 , wherein the cumulative computational credit value is based on the first command type or the second command type.

19. The method of claim 12 , wherein the cumulative computational credit value is based on a data transfer size associated with the memory command, the data transfer size being based on a quantity of logical block addresses indicated in the memory command or a storage size associated with the quantity of logical block addresses.

20. An apparatus, comprising:

means for determining a command type of a memory command to be executed;

means for identifying a first command processor, associated with the command type, from a plurality of command processors associated with executing memory commands,

wherein the first command processor is configured to execute only commands having a first command type unless a first computational credit condition, associated with another command processor of the plurality of command processors, is satisfied;

means for determining a cumulative computational credit value, associated with the first command processor, based on memory commands that are assigned to the first command processor; and

means for determining whether to assign the memory command to the first command processor or a second command processor, of the plurality of command processors, based on whether the cumulative computational credit value satisfies a threshold,

wherein the second command processor is configured to execute only commands having a second command type based on unless a second computational credit condition, associated with another command processor of the plurality of command processors, is satisfied.

21. The apparatus of claim 20 , wherein the apparatus further comprises:

means for detecting a second memory command that is a same command type as the memory command;

means for modifying the cumulative computational credit value; and

means for determining whether to assign the second memory command to the first command processor or the second command processor based on whether the modified cumulative computational credit value satisfies the threshold.

22. The apparatus of claim 20 , wherein the first command type is associated with a first computational credit value and the second command type is associated with a second computational credit value.

23. The apparatus of claim 20 , wherein:

the first command type is a read command type and the second command type is a write command type, or

the first command type is a write command type and the second command type is a read command type,

wherein a computational credit value of the write command type is greater than a computational credit value of the read command type.

24. The apparatus of claim 20 , wherein the cumulative computational credit value is based on memory commands that are assigned to, and not yet executed by, the first command processor.

25. The apparatus of claim 20 , wherein the cumulative computational credit value is based on:

the command type of the memory command, and

a data transfer size indicated in the memory command.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2022
From: SHEN, GUANG; WEI, YUE
To: MICRON TECHNOLOGY, INC.
Reel/Frame 060886/0406 →
Priority Claims (1)
CN 202210998627.5 · Aug 19, 2022 · national
Continuity (1)
Related Publication 20240061585A1 · Feb 22, 2024