Semiconductor memory device with first and second sense amplifiers

1. A semiconductor memory device comprising:

a first word line extending in a first direction;

a second word line provided on one side of the first word line in a second direction and extending in the first direction, the first and second direction crossing each other;

a first memory cell, a gate of the first memory cell being connected to the first word line;

a second memory cell, a gate of the second memory cell being connected to the first word line, the second memory cell being positioned at one side in the first direction with respect to the first memory cell;

a third memory cell, a gate of the third memory cell being connected to the second word line, the third memory cell being positioned at the one side in the second direction with respect to the first memory cell;

a fourth memory cell, a gate of the fourth memory cell being connected to the second word line, the fourth memory cell being positioned at the one side in the first direction with respect to the third memory cell;

a first bit line connected to one end of the first memory cell and one end of the third memory cell, the first bit line extending in the second direction;

a second bit line connected to one end of the second memory cell and one end of the fourth memory cell, the second bit line extending in the second direction;

a first sense amplifier including a first transistor, the first transistor being connected to the first bit line; and

a second sense amplifier including a second transistor, the second transistor being connected to the second bit line,

a first row decoder connected to the first word line, the first row decoder being provided closer to the first memory cell as compared with the second memory cell when viewed in a third direction, the first to third directions crossing one another;

a second row decoder connected to the second word line, the second row decoder being provided closer to the third memory cell as compared with the fourth memory cell when viewed in the third direction,

wherein

during a first read operation to judge data stored in the first memory cell and the second memory cell,

a first voltage is applied to a gate of the first transistor, and

a second voltage different from the first voltage is applied to a gate of the second transistor, and

during a second read operation to judge data stored in the third memory cell and the fourth memory cell,

the second voltage is applied to the gate of the first transistor, and

the first voltage is applied to the gate of the second transistor.

2. The semiconductor memory device according to claim 1 , wherein

the first row decoder and the second row decoder are provided on opposite sides in the first direction when viewed in the third direction.

3. The semiconductor memory device according to claim 2 , wherein

the first row decoder is activated during the first read operation, and

the second row decoder is activated during the second read operation.

4. The semiconductor memory device according to claim 1 , wherein

the first word line includes a first connection portion at one end thereof in the first direction,

the second word line includes a second connection portion at one end thereof in the first direction, the one end of the first word line and the one end of the second word line being provided on opposite sides in the first direction when viewed in the third direction,

the first row decoder is connected to the first connection portion of the first word line, and

the second row decoder is connected to the second connection portion of the second word line.

5. The semiconductor memory device according to claim 1 , further comprising;

a fifth memory cell being connected between the first memory cell and the first bit line;

a sixth memory cell being connected between the second memory cell and the second bit line;

a third word line provided above the first word line in the third direction, the third word line includes a third connection portion at one end thereof in the first direction such that the first connection portion of the first word line is exposed from the third connection portion of the third word line when viewed in the third direction;

wherein

the first row decoder is connected to the first connection portion of the first word line and the third connection portion of the third word line.

6. The semiconductor memory device according to claim 5 , further comprising;

a seventh memory cell being connected between the third memory cell and the first bit line;

an eighth memory cell being connected between the fourth memory cell and the second bit line;

a fourth word line provided above the second word line in the third direction, the fourth word line includes a fourth connection portion at one end thereof in the first direction such that the second connection portion of the second word line is exposed from the fourth connection portion of the fourth word line when viewed in the third direction;

wherein

the second row decoder is connected to the second connection portion of the second word line and the fourth connection portion of the fourth word line.

7. The semiconductor memory device according to claim 1 , wherein

the first voltage is increased with a first rate and decreased with a second rate, and

the second voltage is increased with the first rate and decreased with a third rate gentler than the second rate.

8. The semiconductor memory device according to claim 1 , wherein

each of the first voltage and the second voltage has a waveform which is increased and thereafter gradually decreased, and

the first voltage is decreased faster than the second voltage.

9. The semiconductor memory device according to claim 1 , wherein

each of the first voltage and the second voltage has a waveform which is increased and thereafter decreased in a stepwise manner, and

the first voltage is decreased faster than the second voltage.

10. The semiconductor memory device according to claim 1 , further comprising;

a controller;

a first signal line connected between the controller and the gate of the first transistor of the first sense amplifier; and

a second signal line connected between the controller and the gate of the second transistor of the second sense amplifier.

11. The semiconductor memory device according to claim 10 , wherein

the controller includes a first sub controller and a second sub controller,

the first signal line is connected between the first sub controller and the gate of the first transistor of the first sense amplifier, and

the second signal line is connected between the second sub controller and the gate of the second transistor of the second sense amplifier.

12. The semiconductor memory device according to claim 10 , wherein

the first signal line and the second signal line are disconnected from each other.

13. A method for controlling a semiconductor memory device,

the semiconductor memory including;

a first word line extending in a first direction;

a second word line provided on one side of the first word line in a second direction and extending in the first direction, the first and second direction crossing each other;

a first memory cell, a gate of the first memory cell being connected to the first word line;

a second memory cell, a gate of the second memory cell being connected to the first word line, the second memory cell being positioned at one side in the first direction with respect to the first memory cell;

a third memory cell, a gate of the third memory cell being connected to the second word line, the third memory cell being positioned at the one side in the second direction with respect to the first memory cell;

a fourth memory cell, a gate of the fourth memory cell being connected to the second word line, the fourth memory cell being positioned at the one side in the first direction with respect to the third memory cell;

a first bit line connected to one end of the first memory cell and one end of the third memory cell, the first bit line extending in the second direction;

a second bit line connected to one end of the second memory cell and one end of the fourth memory cell, the second bit line extending in the second direction;

a first sense amplifier including a first transistor, the first transistor being connected to the first bit line; and

a second sense amplifier including a second transistor, the second transistor being connected to the second bit line,

a first row decoder connected to the first word line, the first row decoder being provided closer to the first memory cell as compared with the second memory cell when viewed in a third direction, the first to third directions crossing one another;

a second row decoder connected to the second word line, the second row decoder being provided closer to the third memory cell as compared with the fourth memory cell when viewed in the third direction,

the method comprising;

performing a first read operation to judge data stored in the first memory cell and the second memory cell, by applying a first voltage to a gate of the first transistor, and applying a second voltage different from the first voltage to a gate of the second transistor; and

performing a second read operation to judge data stored in the third memory cell and the fourth memory cell, by applying the second voltage to the gate of the first transistor, and applying the first voltage to the gate of the second transistor.