Gate-all-around integrated circuit structures having germanium-doped nanoribbon channel structures
Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.
1. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a substrate, wherein individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire, wherein individual ones of the vertical arrangement of nanowires have a vertical thickness that grades from relatively thicker at the lateral mid-point of the nanowire to relatively thinner at the lateral ends of the nanowire, and wherein the vertical thickness of each nanowire is 2-10% thicker at the lateral mid-point of the nanowire than at the lateral ends of the nanowire.
2. The integrated circuit structure of claim 1 , wherein the individual ones of the vertical arrangement of nanowires have a relatively lower silicon concentration at the lateral mid-point of the nanowire than at the lateral ends of the nanowire.
3. The integrated circuit structure of claim 2 , wherein the individual ones of the vertical arrangement of nanowires do not include germanium at the lateral ends of the nanowire.
4. The integrated circuit structure of claim 1 , further comprising:
a dielectric cap over the vertical arrangement of nanowires.
5. The integrated circuit structure of claim 1 , further comprising:
a gate stack over the vertical arrangement of nanowires.
6. The integrated circuit structure of claim 1 , further comprising:
epitaxial source or drain structures at the lateral ends of the vertical arrangement of nanowires.
7. The integrated circuit structure of claim 6 , wherein the epitaxial source or drain structures are non-discrete epitaxial source or drain structures.
8. The integrated circuit structure of claim 6 , wherein the epitaxial source or drain structures uniaxially compressively strain the vertical arrangement of nanowires.
9. The integrated circuit structure of claim 1 , wherein the vertical arrangement of nanowires is over a sub-fin.
10. An integrated circuit structure, comprising:
a first vertical arrangement of nanowires above a substrate;
a second vertical arrangement of nanowires stacked vertically with the first vertical arrangement of nanowires, wherein individual ones of the second vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire, wherein individual ones of the second vertical arrangement of nanowires have a vertical thickness that grades from relatively thicker at the mid-point of the nanowire to relatively thinner at the lateral ends of the nanowire, and wherein the vertical thickness of each nanowire is 2-10% thicker at the lateral mid-point of the nanowire than at the lateral ends of the nanowire.
11. The integrated circuit structure of claim 10 , wherein the second vertical arrangement of nanowires is above the first vertical arrangement of nanowires.
12. The integrated circuit structure of claim 10 , wherein the first vertical arrangement of nanowires is above the second vertical arrangement of nanowires.
13. The integrated circuit structure of claim 10 , wherein individual ones of the first vertical arrangement of nanowires consist essentially of silicon.
14. The integrated circuit structure of claim 10 , wherein the individual ones of the second vertical arrangement of nanowires have a relatively lower silicon concentration at the lateral mid-point of the nanowire than at the lateral ends of the nanowire.
15. The integrated circuit structure of claim 14 , wherein the individual ones of the second vertical arrangement of nanowires do not include germanium at the lateral ends of the nanowire.
16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a vertical arrangement of nanowires above a substrate, wherein individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire, wherein individual ones of the vertical arrangement of nanowires have a vertical thickness that grades from relatively thicker at the mid-point of the nanowire to relatively thinner at the lateral ends of the nanowire, and wherein the vertical thickness of each nanowire is 2-10% thicker at the lateral mid-point of the nanowire than at the lateral ends of the nanowire.
17. The computing device of claim 16 , further comprising:
a memory coupled to the board.
18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19. The computing device of claim 16 , further comprising:
a camera coupled to the board.
20. The computing device of claim 16 , further comprising:
a battery coupled to the board.
21. The computing device of claim 16 , further comprising:
an antenna coupled to the board.
22. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
23. The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.