Multi level loopback to enable automated testing of standalone connectivity controller

1. A method of testing a connectivity controller, the method comprising:

setting a configuration register disposed in the connectivity controller to a first value;

causing a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value;

returning data received by the second component, via the first component, for storage in a second section of the memory;

comparing, by a processor, the first data to the data returned and stored in the second section of the memory; and

verifying the test if the first data matches the returned data.

2. The method of claim 1 , wherein the connectivity controller is one or more of a Universal Serial Bus 4 (USB4) host controller and a USB4 device controller.

3. The method of claim 2 , wherein the USB4 controller is configured to process both USB3 generation T packets and USB3 generation X packets.

4. The method of claim 3 , wherein the first component is a USB3 media access controller.

5. The method of claim 4 , wherein the second component is a USB3 link controller.

6. The method of claim 2 further comprising:

validating, by the first component, that a packet represented by the first data conform to the USB4 communications protocols; and

validating, by the second component, that a packet represented by the data returned to the second section of the memory conform the USB4 communications protocol.

7. The method of claim 2 further comprising:

setting the configuration register to a second value;

causing a second data stored in the first section of the first memory to be forwarded to a physical access layer (PHY) of the USB4 controller;

returning data from the PHY for storage in the second section of the memory;

comparing the second data to the data returned from the PHY and stored in the second section of the memory; and

verifying the test if the second data matches the data returned from the PHY.

8. The method of claim 2 , the method further comprising:

setting a direction bit of a packet represented by the first data to a first logic level; and

setting a direction bit of a packet represented by the returned data to a second logic level.

9. A system comprising:

a memory storing instructions; and

a processor, coupled with the memory and configured to execute the instructions, the instructions when executed causing the processor to:

set a configuration register disposed in a connectivity controller to a first value;

cause a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value;

return data received by the second component, via the first component, for storage in a second section of the memory;

compare the first data to the data returned and stored in the second section of the memory; and

verify the test if the first data matches the return data.

10. The system of claim 9 , wherein the connectivity controller is one or more of a USB4 host controller and a USB4 device controller.

11. The system of claim 10 , wherein the USB4 controller is configured to process both USB3 generation T packets and USB3 generation X packets.

12. The hardware emulation system of claim 11 , wherein the first component is a USB3 media access controller.

13. The hardware emulation system of claim 12 , wherein the second component is a USB3 link controller.

14. The system of claim 10 , wherein the USB4 controller comprises a Peripheral Component Interconnect Express (PCIe) controller.

15. The system of claim 10 , wherein the instruction further causes the processor to:

set the configuration register to a second value;

cause a second data stored in the first section of the first memory to be forwarded to a physical access layer (PHY) of the USB4 controller;

return data from the PHY for storage in the second section of the memory;

compare the second data to the data returned from the PHY and stored in the second section of the memory; and

verify the test if the second data matches the data returned from the PHY.

16. The system of claim 10 , wherein the instructions further cause the processor to:

set a direction bit of a packet represented by the first data to a first logic level; and

set a direction bit of a packet represented by the second data to a second logic level.

17. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

set a configuration register disposed in a USB4 controller to a first value;

cause a first data stored in a first section of a memory associated with the USB4 controller to be forwarded and pass through at least a first component of the USB4 controller and a second component of the USB4 controller, in sequence, in response to the first value;

return data received by the second component, via the first component, for storage in a second section of the memory;

compare the first data to the data returned and stored in the second section of the memory; and

verify the test if the first data matches the return data.

18. The non-transitory computer readable medium of claim 17 , wherein the USB4 controller is one or more of a USB4 host controller and a USB4 device controller.

19. The non-transitory computer readable medium of claim 17 , wherein the USB4 controller is configured to process both USB3 generation T packets and USB3 generation X packets.

20. The non-transitory computer readable medium of claim 19 , wherein the instructions further cause the processor:

set a direction bit of a packet represented by the first data to a first logic level; and

set a direction bit of a packet represented by the returned data to a second logic level.