Multi-tile memory management
Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.
1. A graphics processor comprising:
an interposer;
a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and a switched interconnect network coupled with the graphics processing resource;
cache circuitry coupled with the graphics processing resource via the switched interconnect network; and
a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache,
wherein the memory controller is configured to enable access to a high-bandwidth memory (HBM) device,
the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and
the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface, wherein the first chiplet and the second chiplet are distinct and at least partially packaged integrated circuits.
2. The graphics processor of claim 1 , wherein the cache circuitry includes a level-2 (L2) cache.
3. The graphics processor of claim 2 , wherein the L2 cache is a distributed cache having nodes interconnected via the switched interconnect network.
4. The graphics processor of claim 1 , wherein the memory-side cache includes a level-3 (L3) cache.
5. The graphics processor of claim 1 , wherein the interposer, first chiplet, and second chiplet have a 2.5 dimension (2.5D) arrangement and the interposer includes a first standardized slot configured to accept the first chiplet and a second standardized slot configured to accept the second chiplet.
6. The graphics processor of claim 5 , wherein the interposer is an active interposer.
7. The graphics processor of claim 1 , wherein the graphics processing resource includes a plurality of functional units having a single instruction multiple thread (SIMT) architecture.
8. The graphics processor of claim 7 , wherein the plurality of functional units includes a general-purpose graphics processor core and a tensor core.
9. The graphics processor of claim 7 , wherein the plurality of functional units includes a ray-tracing core.
10. The graphics processor of claim 1 , wherein the graphics processing resource includes a plurality of functional units having a single instruction multiple data (SIMD) architecture.
11. A system comprising:
an interconnect to a system interface; and
a multi-die graphics processor coupled with the interconnect, the multi-die graphics processor comprising:
an interposer;
a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and a switched interconnect network coupled with the graphics processing resource;
cache circuitry coupled with the graphics processing resource via the switched interconnect network; and
a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache, wherein the memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface, wherein the first chiplet and the second chiplet are distinct and at least partially packaged integrated circuits.
12. The system of claim 11 , wherein the cache circuitry includes a level-2 (L2) cache.
13. The system of claim 12 , wherein the L2 cache is a distributed cache having nodes interconnected via the switched interconnect network.
14. The system of claim 11 , wherein the memory-side cache includes a level-3 (L3) cache.
15. The system of claim 11 , wherein the interposer, first chiplet, and second chiplet have a 2.5 dimension (2.5D) arrangement and the interposer includes a first standardized slot configured to accept the first chiplet and a second standardized slot configured to accept the second chiplet.
16. The system of claim 15 , wherein the interposer is an active interposer.
17. The system of claim 11 , wherein the graphics processing resource includes a plurality of functional units having a single instruction multiple thread (SIMT) architecture.
18. The system of claim 17 , wherein the plurality of functional units includes a general-purpose system core and a tensor core.
19. The system of claim 17 , wherein the plurality of functional units includes a ray-tracing core.
20. The system of claim 11 , wherein the graphics processing resource includes a plurality of functional units having a single instruction multiple data (SIMD) architecture.