IP Library Granted Patent US 12,210,321
Granted Patent B2
US 12,210,321 · App. 18/069,662 · Granted Jan 28, 2025

Methods and apparatus for a time-to-digital converter

Inventor: Anthony Richard Huggett (Tadley, GB)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G04F10/005G01S7/4861G01S17/10
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Quick Facts
Patent No.
US 12,210,321
App. No.
18/069,662
Granted
Jan 28, 2025
Kind
B2
Abstract

Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.

Claims (11)

1. A system comprising:

a pixel that comprises a single-photon avalanche diode, wherein the pixel is configured to output an event signal that has a first value when a photon is detected by the single-photon avalanche diode and a second value when no photons are detected by the single-photon avalanche diode; and

a time-to-digital converter comprising a state machine, wherein the state machine is configured to receive the event signal from the pixel and change to a new state based at least on a current state and the event signal.

2. The system defined in claim 1 , wherein the state machine is a Markov state machine.

3. The system defined in claim 1 , wherein the state machine is configured to initialize to a state, increment the state when the event signal has the first value, and decrement the state when the event signal has the second value.

4. The system defined in claim 3 , wherein the first value is 1 and wherein the second value is 0.

5. The system defined in claim 4 , wherein initializing to a state comprises initializing to 0.

6. The system defined in claim 1 , wherein the time-to-digital converter comprises:

a range register that is configured to receive a count value from a counter.

7. The system defined in claim 1 , wherein the time-to-digital converter comprises:

a comparator connected to an output terminal of the state machine and configured to compare a current state of the state machine to a starting state.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 062882, FRAME 0265 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0423 →
SECURITY INTEREST Recorded Feb 24, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 062882/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2022
From: HUGGETT, ANTHONY RICHARD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 062174/0201 →