Write booster buffer flush operation
Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.
1. A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
receive a command to transfer information from a write booster buffer to a storage space of the one or more memory devices, the write booster buffer comprising a first plurality of blocks and the storage space comprising a second plurality of blocks;
reassign, based at least in part on receiving the command, a valid block of the write booster buffer to the storage space and an invalid block of the storage space to the write booster buffer, the valid block storing a portion of the information stored in the write booster buffer and the invalid block available to store information, wherein the reassigning is based at least in part on a quantity of invalid blocks of the storage space satisfying a threshold quantity of invalid blocks, the threshold quantity being associated with a quantity of blocks of the quantity of invalid blocks triggering a garbage collection operation on the storage space; and
transfer the portion of the information stored in the valid block to a block of multiple level memory cells of the storage space after reassigning the valid block to the storage space and reassigning the invalid block to the write booster buffer.
2. The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
determine whether a first quantity of invalid blocks of the storage space satisfies the threshold quantity of invalid blocks of the storage space, wherein reassigning the valid block and the invalid block is based at least in part on determining that the first quantity of invalid blocks satisfies the threshold quantity of invalid blocks.
3. The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
determine a second quantity of invalid blocks of the storage space that exceeds the threshold quantity of invalid blocks, wherein reassigning the valid block comprises reassigning a second quantity of valid blocks of the write booster buffer and reassigning the invalid block comprises reassigning the second quantity of the invalid blocks of the storage space.
4. The memory system of claim 2 , wherein the threshold quantity of invalid blocks of the storage space is associated with a quantity of invalid blocks used to trigger a garbage collection operation.
5. The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
determine whether the write booster buffer includes one or more valid blocks that store portions of the information after reassigning the valid block to the storage space; and
reassign, based at least in part on determining that the write booster buffer includes the one or more valid blocks, a second set of valid blocks from the write booster buffer to the storage space and a second set of invalid blocks from the storage space to the write booster buffer.
6. The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
enter, by the one or more memory devices, a state associated with performing a flush operation associated with the command to transfer the information from the write booster buffer to the storage space based at least in part on receiving the command, wherein reassigning the valid block and the invalid block is based at least in part on entering the state.
7. The memory system of claim 6 , wherein:
the command comprises a write booster buffer flush during hibernate flag; and
the state comprises a hibernate state of the one or more memory devices.
8. The memory system of claim 6 , wherein:
the command comprises a write booster buffer flush enable flag; and
the state comprises an idle state of the one or more memory devices.
9. The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
determine whether a command buffer associated with commands received from a host system and waiting to be executed by the one or more memory devices is empty, wherein reassigning the valid block and the invalid block is based at least in part on determining that the command buffer is empty.
10. The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
transmit, to a host system, a notification of a status of a flush operation for the write booster buffer based at least in part on reassigning the valid block and the invalid block, wherein the notification comprises an indication that a flush operation associated with the command is in progress, an indication that the flush operation ended before completion, or an indication that the flush operation is complete.
11. The memory system of claim 10 , wherein the one or more controllers are further configured to cause the memory system to:
determine whether the write booster buffer is empty of the information, wherein transmitting the notification is based at least in part on determining that the write booster buffer is empty.
12. The memory system of claim 1 , wherein:
the write booster buffer comprises a first plurality of single-level cell (SLC) blocks; and
the storage space comprising a second plurality of triple-level cell (TLC) blocks.
13. The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
receive an activate command to write information to the write booster buffer;
receive a write command to store information in the one or more memory devices; and
write the information associated with the write command to an invalid block of the write booster buffer based at least in part on receiving the activate command and receiving the write command, wherein receiving the command is based at least in part on writing the information.
14. The memory system of claim 13 , wherein the one or more controllers are further configured to cause the memory system to:
determine whether the write booster buffer includes one or more invalid blocks available to store information, wherein writing the information to the write booster buffer is based at least in part on determining that the write booster buffer includes the one or more invalid blocks.
15. A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of an electronic device, cause the electronic device to:
receive a command to transfer information from a write booster buffer to a storage space of a memory device, the write booster buffer comprising a first plurality of blocks and the storage space comprising a second plurality of blocks;
reassign, based at least in part on receiving the command, a valid block of the write booster buffer to the storage space and an invalid block of the storage space to the write booster buffer, the valid block storing a portion of the information stored in the write booster buffer and the invalid block available to store information, wherein the reassigning is based at least in part on a quantity of invalid blocks of the storage space satisfying a threshold quantity of invalid blocks, the threshold quantity being associated with a quantity of blocks of the quantity of invalid blocks triggering a garbage collection operation on the storage space; and
transfer the portion of the information stored in the valid block to a block of multiple level memory cells of the storage space after reassigning the valid block to the storage space and reassigning the invalid block to the write booster buffer.
16. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to:
determine whether a first quantity of invalid blocks of the storage space satisfies the threshold quantity of invalid blocks of the storage space, wherein reassigning the valid block and the invalid block is based at least in part on determining that the first quantity of invalid blocks satisfies the threshold quantity of invalid blocks.
17. The non-transitory computer-readable medium of claim 16 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to:
determine a second quantity of invalid blocks of the storage space that exceeds the threshold quantity of invalid blocks, wherein reassigning the valid block comprises reassigning a second quantity of valid blocks of the write booster buffer and reassigning the invalid block comprises reassigning the second quantity of the invalid blocks of the storage space.
18. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to:
determine whether the write booster buffer includes one or more valid blocks that store portions of the information after reassigning the valid block to the storage space; and
reassign, based at least in part on determining that the write booster buffer includes the one or more valid blocks, a second set of valid blocks from the write booster buffer to the storage space and a second set of invalid blocks from the storage space to the write booster buffer.
19. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to:
enter, by the memory device, a state associated with performing a flush operation associated with the command to transfer the information from the write booster buffer to the storage space based at least in part on receiving the command, wherein reassigning the valid block and the invalid block is based at least in part on entering the state.
20. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to:
transmit, to a host system, a notification of a status of a flush operation for the write booster buffer based at least in part on reassigning the valid block and the invalid block, wherein the notification comprises an indication that a flush operation associated with the command is in progress, an indication that the flush operation ended before completion, or an indication that the flush operation is complete.
21. A method performed by a memory system, comprising:
receiving a command to transfer information from a write booster buffer to a storage space of a memory device, the write booster buffer comprising a first plurality of blocks and the storage space comprising a second plurality of blocks;
reassigning, based at least in part on receiving the command, a valid block of the write booster buffer to the storage space and an invalid block of the storage space to the write booster buffer, the valid block storing a portion of the information stored in the write booster buffer and the invalid block available to store information, wherein the reassigning is based at least in part on a quantity of invalid blocks of the storage space satisfying a threshold quantity of invalid blocks, the threshold quantity being associated with a quantity of blocks of the quantity of invalid blocks triggering a garbage collection operation on the storage space; and
transferring the portion of the information stored in the valid block to a block of multiple level memory cells of the storage space after reassigning the valid block to the storage space and reassigning the invalid block to the write booster buffer.
22. The method of claim 21 , further comprising:
determining whether a first quantity of invalid blocks of the storage space satisfies the threshold quantity of invalid blocks of the storage space, wherein reassigning the valid block and the invalid block is based at least in part on determining that the first quantity of invalid blocks satisfies the threshold quantity of invalid blocks.
23. The method of claim 22 , further comprising:
determining a second quantity of invalid blocks of the storage space that exceeds the threshold quantity of invalid blocks, wherein reassigning the valid block comprises reassigning a second quantity of valid blocks of the write booster buffer and reassigning the invalid block comprises reassigning the second quantity of the invalid blocks of the storage space.
24. The method of claim 21 , further comprising:
determining whether the write booster buffer includes one or more valid blocks that store portions of the information after reassigning the valid block to the storage space; and
reassigning, based at least in part on determining that the write booster buffer includes the one or more valid blocks, a second set of valid blocks from the write booster buffer to the storage space and a second set of invalid blocks from the storage space to the write booster buffer.
25. The method of claim 21 , further comprising:
entering, by the memory device, a state associated with performing a flush operation associated with the command to transfer the information from the write booster buffer to the storage space based at least in part on receiving the command, wherein reassigning the valid block and the invalid block is based at least in part on entering the state.