Granted Patent B2

US 12,218,849 · App. 18/589,466 · Granted Feb 4, 2025

Inventors: Roni Bar Yanai (Even Yehuda, IL); Jiawei Wang (Shenzhen, CN); Yossef Efraim (Hong Kong Island, HK); Chen Rozenbaum (Beer Yaakov, IL)

Assignee: Mellanox Technologies, Ltd

H04L47/2483H04L45/748

Abstract

Claims (75)

1. A method, comprising:

providing a library of hardware-agnostic packet-processing functions;

receiving, from a user, a functional hardware-agnostic specification of a packet-processing pipeline, the specification defined in terms of one or more of the packet-processing functions drawn from the library;

deriving, from the functional hardware-agnostic specification, a hardware-specific design of the packet-processing pipeline that is suited to manufacture a hardware device implementing the packet-processing pipeline, wherein deriving the hardware-specific design comprises (i) converting the functional hardware-agnostic specification into a hardware-agnostic intermediate representation, and (ii) generating the hardware-specific design from the intermediate representation; and

adding a new function or flow-pipe to the hardware-specific design, by:

converting a new functional hardware-agnostic specification, of the new function or flow-pipe, into the intermediate representation; and

generating an updated hardware-specific design, which includes the new function or flow-pipe, from (i) the intermediate representation of the functional hardware-agnostic specification of the packet-processing pipeline and (ii) the intermediate representation of the new function or flow-pipe.

2. The method according to claim 1 , wherein providing the library comprises exposing to the user an Application Programming Interface (API) for defining the specification using the library.

3. The method according to claim 1 , wherein the hardware-agnostic packet-processing functions perform one or more of:

Access Control List (ACL) functionality;

Longest Prefix Matching (LPM);

match table functionality;

encryption;

decryption;

packet modification;

packet mirroring;

packet metering;

packet counting;

connection tracking;

packet aging; and

packet forwarding.

4. The method according to claim 1 , wherein at least one of the hardware-agnostic packet-processing functions comprises a user-configurable packet parsing operation, and wherein receiving the specification from the user comprises receiving a configuration of the packet parsing operation.

5. The method according to claim 1 , wherein at least one of the hardware-agnostic packet-processing functions comprises a user-configurable action, and wherein receiving the specification from the user comprises receiving a configuration of the action.

6. The method according to claim 1 , wherein deriving the hardware-specific design of the packet-processing pipeline comprises deriving a design of one of a switch, a router, a gateway, a network adapter, a firewall and a User-Plane Function (UPF).

7. An apparatus, comprising:

a memory, to store a library of hardware-agnostic packet-processing functions; and

a processor, to:

provide the library to a user;

receive, from the user, a functional hardware-agnostic specification of a packet-processing pipeline, the specification defined in terms of one or more of the packet-processing functions drawn from the library;

derive, from the functional hardware-agnostic specification, a hardware-specific design of the packet-processing pipeline that is suited to manufacture a hardware device implementing the packet-processing pipeline, wherein, to derive the hardware-specific design, the processor is to (i) convert the functional hardware-agnostic specification into a hardware-agnostic intermediate representation, and (ii) generate the hardware-specific design from the intermediate representation; and

add a new function or flow-pipe to the hardware-specific design, by:

converting a new functional hardware-agnostic specification, of the new function or flow-pipe, into the intermediate representation; and

generating an updated hardware-specific design, which includes the new function or flow-pipe, from (i) the intermediate representation of the functional hardware-agnostic specification of the packet-processing pipeline and (ii) the intermediate representation of the new function or flow-pipe.

8. The apparatus according to claim 7 , wherein the processor is to expose to the user an Application Programming Interface (API) for defining the specification using the library.

9. The apparatus according to claim 7 , wherein the hardware-agnostic packet-processing functions perform one or more of:

Access Control List (ACL) functionality;

Longest Prefix Matching (LPM);

match table functionality;

encryption;

decryption;

packet modification;

packet mirroring;

packet metering;

packet counting;

connection tracking;

packet aging; and

packet forwarding.

10. The apparatus according to claim 7 , wherein at least one of the hardware-agnostic packet-processing functions comprises a user-configurable packet parsing operation, and wherein, in receiving the specification from the user, the processor is to receive a configuration of the packet parsing operation.

11. The apparatus according to claim 7 , wherein at least one of the hardware-agnostic packet-processing functions comprises a user-configurable action, and wherein, in receiving the specification from the user, the processor is to receive a configuration of the action.

12. The apparatus according to claim 7 , wherein the processor is to derive, from the specification, a hardware-specific design of one of a switch, a router, a gateway, a network adapter, a firewall and a User-Plane Function (UPF).

13. A computer software product, the product comprising a tangible non-transitory computer-readable medium in which program instructions are stored, which instructions, when read by a processor, cause the processor to:

store a library of hardware-agnostic packet-processing functions;

provide the library to a user;

receive, from the user, a functional hardware-agnostic specification of a packet-processing pipeline, the specification defined in terms of one or more of the packet-processing functions drawn from the library;

derive, from the functional hardware-agnostic specification, a hardware-specific design of the packet-processing pipeline that is suited to manufacture a hardware device implementing the packet-processing pipeline, wherein, to derive the hardware-specific design, the instructions cause the processor to (i) convert the functional hardware-agnostic specification into a hardware-agnostic intermediate representation, and (ii) generate the hardware-specific design from the intermediate representation; and

add a new function or flow-pipe to the hardware-specific design, by:

converting a new functional hardware-agnostic specification, of the new function or flow-pipe, into the intermediate representation; and

generating an updated hardware-specific design, which includes the new function or flow-pipe, from (i) the intermediate representation of the functional hardware-agnostic specification of the packet-processing pipeline and (ii) the intermediate representation of the new function or flow-pipe.

14. The product according to claim 13 , wherein the instructions cause the processor to expose to the user an Application Programming Interface (API) for defining the specification using the library.

15. The product according to claim 13 , wherein the hardware-agnostic packet-processing functions perform one or more of:

Access Control List (ACL) functionality;

Longest Prefix Matching (LPM);

match table functionality;

encryption;

decryption;

packet modification;

packet mirroring;

packet metering;

packet counting;

connection tracking;

packet aging; and

packet forwarding.

16. The product according to claim 13 , wherein at least one of the hardware-agnostic packet-processing functions comprises a user-configurable packet parsing operation, and wherein the instructions cause the processor to receive from the user a configuration of the packet parsing operation.

17. The product according to claim 13 , wherein at least one of the hardware-agnostic packet-processing functions comprises a user-configurable action, and wherein the instructions cause the processor to receive from the user a configuration of the action.

18. The product according to claim 13 , wherein the instructions cause the processor to derive, from the specification, a hardware-specific design of one of a switch, a router, a gateway, a network adapter, a firewall and a User-Plane Function (UPF).

Assignments (1)

Continuity (3)

References Cited (20)