Clock signal skew calibration apparatus and control method
An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
1. An apparatus comprising:
a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises:
a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals;
a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicating a skew of a first multi-phase clock signal; and
a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
2. The apparatus of claim 1 , wherein a second clock skew calibration unit of the clock skew calibration circuit comprises:
a first logic gate configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal;
a second logic gate configured to perform a second AND operation on a reference multi-phase clock signal and the second multi-phase clock signal; and
a first comparator configured to compare an output of the first logic gate with an output of the second logic gate, and generate a second control signal to adjust a skew of the second multi-phase clock signal through adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved.
3. The apparatus of claim 2 , wherein a third clock skew calibration unit of the clock skew calibration circuit comprises:
a third logic gate configured to perform a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal;
a fourth logic gate configured to perform a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal; and
a second comparator configured to compare an output of the third logic gate with an output of the fourth logic gate, and generate a third control signal to adjust a skew of the third multi-phase clock signal through adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.
4. The apparatus of claim 3 , wherein:
the multi-phase clock generator is configured to generate 4-phase clock signals comprising a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal and a 270-degree clock signal, and wherein:
the reference multi-phase clock signal is the 0-degree clock signal;
the first multi-phase clock signal is the 180-degree clock signal;
the second multi-phase clock signal is the 90-degree clock signal; and
the third multi-phase clock signal is the 270-degree clock signal.
5. The apparatus of claim 1 , wherein the frequency doubler comprises a first transmission gate and a second transmission gate, and wherein:
an input of the first transmission gate is configured to receive the 0-degree clock signal;
an output of the first transmission gate is connected to an output of the frequency doubler;
a first control terminal of the first transmission gate is configured to receive the 90-degree clock signal;
a second control terminal of the first transmission gate is configured to receive the 270-degree clock signal;
an input of the second transmission gate is configured to receive the 180-degree clock signal;
an output of the second transmission gate is connected to the output of the frequency doubler;
a first control terminal of the second transmission gate is configured to receive the 270-degree clock signal;
a second control terminal of the second transmission gate is configured to receive the 90-degree clock signal.
6. The apparatus of claim 1 , wherein the first clock skew calibration unit further comprises:
a latch circuit configured to generate a direction control signal; and
a filter configured to receive the reduced frequency signal and generate a dc signal, wherein a voltage of the de signal is proportional to the duty cycle of the reduced frequency signal.
7. The apparatus of claim 6 , wherein the delay line control circuit comprises an inverter, a first switch, a second switch, a third switch, a fourth switch and a third comparator, and wherein:
the inverter is configured to receive the direction control signal and generate an inverted signal of the direction control signal;
a first drain/source terminal of the first switch is configured to receive the dc signal;
a second drain/source terminal of the first switch is connected to a non-inverting input of the third comparator;
a gate of the first switch is controlled by the direction control signal;
a first drain/source terminal of the second switch is configured to receive a reference voltage proportional to the predetermined duty cycle;
a second drain/source terminal of the second switch is connected to the non-inverting input of the third comparator;
a gate of the second switch is controlled by the inverted signal of the direction control signal;
a first drain/source terminal of the third switch is configured to receive the de signal;
a second drain/source terminal of the third switch is connected to an inverting input of the third comparator;
a gate of the third switch is controlled by the inverted signal of the direction control signal;
a first drain/source terminal of the fourth switch is configured to receive the reference voltage proportional to the predetermined duty cycle;
a second drain/source terminal of the fourth switch is connected to the inverting input of the third comparator;
a gate of the fourth switch is controlled by the direction control signal; and
an output of the third comparator is configured to generate the first control signal.
8. The apparatus of claim 1 , wherein the first delay is generated by a first delay line, and wherein the first delay line comprises:
a biasing circuit comprising an upper transistor and a lower transistor connected in series between a supply voltage and ground; and
a plurality of inverting legs connected in parallel between the supply voltage and ground, and wherein each inverting leg comprises a first transistor, a second transistor, a third transistor and a fourth transistor connected in series, and wherein:
a gate of the first transistor is connected to a gate of the upper transistor;
a gate of the second transistor and a gate of the third transistor are connected together and function as an input of an inverting leg, and a midpoint of the inverting leg functions as an output of the inverting leg, and
a gate of the fourth transistor is connected to a gate of the lower transistor, and wherein:
an input of a first inverting leg of the plurality of inverting legs is configured to receive the first multi-phase clock signal;
an output of the first inverting leg of the plurality of inverting legs is connected to an input of a second inverting leg of the plurality of inverting legs; and
an output of a last inverting leg of the plurality of inverting legs is configured to generate the calibrated signal of the first multi-phase clock signal.
9. A method comprising:
generating, by a frequency doubler, a clock signal based on a plurality of multi-phase clock signals;
generating, by a frequency divider, a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicating a skew of a first multi-phase clock signal;
comparing the duty cycle of the reduced frequency signal with a predetermined duty cycle; and
generating, by a delay line control circuit, a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
10. The method of claim 9 , further comprising:
performing a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal;
performing a second AND operation on a reference multi-phase clock signal and the second multi-phase clock signal; and
comparing a result of the first AND operation with a result of the second AND operation; and
based on a comparison result from the step of comparing the result of the first AND operation with the result of the second AND operation, generating a second control signal to adjust a skew of the second multi-phase clock signal through adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved.
11. The method of claim 10 , further comprising:
performing a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal;
performing a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal; and
comparing a result of the third AND operation with a result of the fourth AND operation; and
based on a comparison result from the step of comparing the result of the third AND operation with the result of the fourth AND operation, generating a third control signal to adjust a skew of the third multi-phase clock signal through adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.
12. The method of claim 11 , further comprising:
generating, by a multi-phase clock generator, 4-phase clock signals comprising a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal and a 270-degree clock signal, wherein:
the reference multi-phase clock signal is the 0-degree clock signal;
the first multi-phase clock signal is the 180-degree clock signal;
the second multi-phase clock signal is the 90-degree clock signal; and
the third multi-phase clock signal is the 270-degree clock signal.
13. The method of claim 12 , wherein the multi-phase clock generator comprises a first oscillator, a second oscillator, a third oscillator and a fourth oscillator connected in cascade, and wherein:
an inverting output of the first oscillator is connected to a non-inverting input of the second oscillator, wherein the inverting output of the first oscillator is configured to generate the 270-degree clock signal;
a non-inverting output of the first oscillator is connected to an inverting input of the second oscillator;
an inverting output of the second oscillator is connected to a non-inverting input of the third oscillator, wherein the inverting output of the second oscillator is configured to generate the 180-degree clock signal;
a non-inverting output of the second oscillator is connected to an inverting input of the third oscillator;
an inverting output of the third oscillator is connected to a non-inverting input of the fourth oscillator, wherein the inverting output of the third oscillator is configured to generate the 90-degree clock signal;
a non-inverting output of the third oscillator is connected to an inverting input of the fourth oscillator;
an inverting output of the fourth oscillator is connected to a non-inverting input of the first oscillator, wherein the inverting output of the fourth oscillator is configured to generate the 0-degree clock signal; and
a non-inverting output of the fourth oscillator is connected to an inverting input of the first oscillator.
14. The method of claim 12 , wherein:
the frequency divider is a latch circuit; and
the frequency doubler comprises a first transmission gate and a second transmission gate, and wherein:
an input of the first transmission gate is configured to receive the 0-degree clock signal;
an output of the first transmission gate is connected to an output of the frequency doubler;
a first control terminal of the first transmission gate is configured to receive the 90-degree clock signal;
a second control terminal of the first transmission gate is configured to receive the 270-degree clock signal;
an input of the second transmission gate is configured to receive the 180-degree clock signal;
an output of the second transmission gate is connected to the output of the frequency doubler;
a first control terminal of the second transmission gate is configured to receive the 270-degree clock signal; and
a second control terminal of the second transmission gate is configured to receive the 90-degree clock signal.
15. The method of claim 9 , further comprising:
converting the reduced frequency signal into a de signal, wherein a voltage of the dc signal is proportional to the duty cycle of the reduced frequency signal; and
comparing the voltage of the de signal with a reference voltage proportional to the predetermined duty cycle to obtain the first control signal.
16. The method of claim 15 , wherein the delay line control circuit comprises an inverter, a first switch, a second switch, a third switch, a fourth switch and a third comparator, and wherein:
the inverter is configured to receive a direction control signal and generate an inverted signal of the direction control signal;
a first drain/source terminal of the first switch is configured to receive the de signal;
a second drain/source terminal of the first switch is connected to a non-inverting input of the third comparator;
a gate of the first switch is controlled by the direction control signal;
a first drain/source terminal of the second switch is configured to receive the reference voltage proportional to the predetermined duty cycle;
a second drain/source terminal of the second switch is connected to the non-inverting input of the third comparator;
a gate of the second switch is controlled by the inverted signal of the direction control signal;
a first drain/source terminal of the third switch is configured to receive the dc signal;
a second drain/source terminal of the third switch is connected to an inverting input of the third comparator;
a gate of the third switch is controlled by the inverted signal of the direction control signal;
a first drain/source terminal of the fourth switch is configured to receive the reference voltage proportional to the predetermined duty cycle;
a second drain/source terminal of the fourth switch is connected to the inverting input of the third comparator;
a gate of the fourth switch is controlled by the direction control signal; and
an output of the third comparator is configured to generate the first control signal.
17. A system comprising:
a multi-phase clock generator configured to generate a plurality of multi-phase clock signals;
a plurality of delay lines configured to receive respective multi-phase clock signals; and
a clock skew calibration circuit configured to be coupled to the multi-phase clock generator through the plurality of delay lines, wherein of the clock skew calibration circuit comprises a first clock skew calibration unit, a second clock skew calibration unit and a third clock skew calibration unit, and wherein the first clock skew calibration unit comprises:
a frequency doubler configured to receive the plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals;
a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicating a skew of a first multi-phase clock signal; and
a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
18. The system of claim 17 , wherein:
the second clock skew calibration unit of the clock skew calibration circuit comprises:
a first logic gate configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal;
a second logic gate configured to perform a second AND operation on a reference multi-phase clock signal and the second multi-phase clock signal; and
a first comparator configured to compare an output of the first logic gate with an output of the second logic gate, and generate a second control signal to adjust a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved; and
the third clock skew calibration unit of the clock skew calibration circuit comprises:
a third logic gate configured to perform a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal;
a fourth logic gate configured to perform a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal; and
a second comparator configured to compare an output of the third logic gate with an output of the fourth logic gate, and generate a third control signal to adjust a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.
19. The system of claim 18 , wherein:
the multi-phase clock generator is configured to generate 4-phase clock signals comprising a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal and a 270-degree clock signal, and wherein:
the reference multi-phase clock signal is the 0-degree clock signal;
the first multi-phase clock signal is the 180-degree clock signal;
the second multi-phase clock signal is the 90-degree clock signal; and
the third multi-phase clock signal to be calibrated is the 270-degree clock signal.
20. The system of claim 19 , wherein:
a first delay line of the plurality of delay lines is configured to receive the 0-degree clock signal and a predetermined reference signal, and add a predetermined delay into the 0-degree clock signal based on the predetermined reference signal;
a second delay line of the plurality of delay lines is configured to receive the 180-degree clock signal and the first control signal, and add the first delay into the 180-degree clock signal based on the first control signal;
a third delay line of the plurality of delay lines is configured to receive the 90-degree clock signal and the second control signal, and add the second delay into the 90-degree clock signal based on the second control signal; and
a fourth delay line of the plurality of delay lines is configured to receive the 270-degree clock signal and the third control signal, and add the third delay into the 270-degree clock signal based on the third control signal.