Granted Patent B2

US 12,248,564 · App. 18/625,085 · Granted Mar 11, 2025

Inventors: Steven Milburn (Cranston, RI); Eli Boling (Manchester, MA)

Assignee: Dover Microsystems, Inc.

G06F21/54G06F9/30058G06F9/30101G06F9/3017G06F9/3806G06F21/121

Abstract

Claims (73)

1. A system comprising:

metadata processing hardware and at least one processor programed by executable instructions to process metadata, wherein the metadata processing hardware and the at least one programmed processor are configured to:

receive first instruction information associated with at least one first instruction executed by a host processor, wherein the at least one first instruction is part of a first instruction path;

use the first instruction information to obtain first metadata associated with the at least one first instruction;

use the first metadata to transform the first instruction information into second instruction information, wherein:

the second instruction information is associated a second instruction path;

an execution of the first instruction path and an execution of the second instruction path have a same effect on one or more hardware entities and one or more memory locations; and the second instruction path represents fewer operations than the first instruction path; and use second metadata associated with the second instruction information to determine whether the at least one first instruction is allowable for execution according to at least one policy; and in response to determining that the at least one first instruction is allowable, provide, to an interlock, an indication to release a queued result of executing the at least one first instruction for use by the system.

2. The system of claim 1 , wherein the metadata processing hardware and the at least one programmed processor are further configured to:

use the first metadata to obtain the second metadata used to determine whether the at least one first instruction is allowable.

3. The system of claim 2 , wherein:

the first metadata comprises at least one pointer to at least one data structure comprising:

the second instruction information; and

the second metadata associated with the second instruction information.

4. The system of claim 1 , wherein:

the first instruction path is convertible into the second instruction path.

5. The system of claim 1 , wherein:

the execution of the first instruction path and the execution of the second instruction path have a same input-output behavior.

6. The system of claim 1 , wherein:

the at least one first instruction comprises a branch instruction that is part of the first instruction path; and

the second instruction path comprises:

a result of removing one or more instructions from the first instruction path; and a result of replacing the one or more instructions in the first instruction path with one or more other instructions, wherein the one or more instructions and the one or more other instructions represent a same operation.

7. The system of claim 1 , wherein the metadata processing hardware and the at least one programmed processor are further configured to:

determine third metadata using the second instruction information and the second metadata; and

update at least one metadata storage location using the third metadata.

8. The system of claim 7 , wherein:

the at least one metadata storage location comprises at least one location selected from a group consisting of: a tag map table location, a hardware register location, and a metadata memory location.

9. The system of claim 7 , wherein:

the metadata processing hardware is configured to:

receive the first instruction information; and

in response to receiving the first instruction information, query the at least one programmed processor to validate the at least one first instruction; and

the at least one programmed processor is configured to:

receive the query; and

determine the third metadata in response to the query.

10. The system of claim 7 , wherein:

the at least one programmed processor is configured to:

provide, to the metadata processing hardware, at least one rule for use in determining the third metadata; and

the metadata processing hardware is configured to:

receive the at least one rule;

evaluate the at least one rule to determine the third metadata; and

update the at least one metadata storage location using the third metadata.

11. The system of claim 9 , wherein:

the at least one programmed processor is further configured to:

update the at least one metadata storage location using the third metadata.

12. The system of claim 7 , wherein:

the second instruction path comprises an inserted instruction to effectuate updating the at least one metadata storage location.

13. The system of claim 7 , wherein:

the metadata processing hardware and the at least one programmed processor are configured to implement a stack policy indicating read-only access, by one or more instructions within a body of a function during a call to the function, to one or more locations in a call stack associated with a metadata tag;

the at least one first instruction indicates completion of a call to the function; and

updating the at least one metadata storage location using the third metadata results in the metadata tag being disassociated from the one or more locations in the call stack.

14. The system of claim 1 , wherein:

the at least one first instruction is in a host Instruction Set Architecture (ISA) used by the host processor;

the second instruction information comprises a translation of at least a portion of the first instruction information, the translation not in the host ISA;

the first instruction information further comprises an address of the at least one first instruction;

the second metadata is obtained using the address of the at least one first instruction.

15. The system of claim 14 , wherein:

the translation of at least a portion of the first instruction information is in a policy engine ISA.

16. The system of claim 14 , wherein:

the metadata processing hardware and the at least one programmed processor are further configured to generate the translation of at least a portion of the first instruction information at least in part by converting the at least one first instruction in the host ISA to at least one second instruction in a policy engine ISA according to a mapping implemented using a look-up table, a field-programmable gate array, or dedicated logic circuitry.

17. The system of claim 14 , wherein:

the metadata processing hardware and the at least one programmed processor are further configured to generate the translation of at least a portion of the first instruction information at least in party by identifying at least one data structure comprising at least one instruction in a policy engine ISA, and

the translation of at least a portion of the first instruction information comprises the at least one instruction in the policy engine ISA.

18. A method performed by a system comprising metadata processing hardware and at least one processor programed by executable instructions to process metadata, the method comprising:

receiving first instruction information associated with at least one first instruction executed by a host processor, wherein the at least one first instruction is part of a first instruction path;

using the first instruction information to obtain first metadata associated with the at least one first instruction;

using the first metadata to transform the first instruction information into second instruction information, wherein:

the second instruction information is associated a second instruction path;

an execution of the first instruction path and an execution of the second instruction path have a same effect on one or more hardware entities and one or more memory locations; and the second instruction path represents fewer operations than the first instruction path; and using second metadata associated with the second instruction information to determine whether the at least one first instruction is allowable for execution according to at least one policy; and in response to determining that the at least one first instruction is allowable, providing, to an interlock, an indication to release a queued result of executing the at least one first instruction for use by the system.

19. At least one non-transitory computer-readable medium having encoded thereon instructions which, when executed by at least one processor of a system, cause the at least one processor to perform an operation comprising:

receiving first instruction information associated with at least one first instruction executed by a host processor, wherein the at least one first instruction is part of a first instruction path;

using the first instruction information to obtain first metadata associated with the at least one first instruction;

using the first metadata to transform the first instruction information into second instruction information, wherein:

the second instruction information is associated a second instruction path;

an execution of the first instruction path and an execution of the second instruction path have a same effect on one or more hardware entities and one or more memory locations; and the second instruction path represents fewer operations than the first instruction path; and using second metadata associated with the second instruction information to determine whether the at least one first instruction is allowable for execution according to at least one policy; and in response to determining that the at least one first instruction is allowable, providing, to an interlock, an indication to release a queued result of executing the at least one first instruction for use by the system.

Assignments (1)

Continuity (5)

References Cited (400)