Single bitline SRAM pixel and method for driving the same

1. A bit storage circuit comprising:

a first voltage supply line;

a second voltage supply line;

a bit line;

a latch having an input and an output;

a first switching transistor having a first terminal, a second terminal, and a control terminal, said first switching transistor being operative to selectively provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a first control signal being asserted on said control terminal of said first switching transistor;

a blocking transistor including a control terminal and being operative to selectively provide a conductive path and a non-conductive path between said input of said latch and said second voltage supply line responsive to a second control signal; and

a second switching transistor having a first terminal, a second terminal, and a control terminal, said second switching transistor being operative to selectively provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a third control signal being asserted on said control terminal of said second switching transistor; and wherein

said first switching transistor and said second switching transistor are coupled in series between said bit line and said input of said latch; and

said bit storage circuit is connected to no more than one bit line.

2. The bit storage circuit of claim 1 , wherein said latch includes:

a first p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;

a first n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;

a second p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch; and

a second n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal selectively coupled to said input of said latch via said blocking transistor, and a gate terminal coupled to said output of said latch.

3. The bit storage circuit of claim 1 , wherein said latch includes:

a first p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;

a first n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;

a second p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch; and

a second n-channel transistor having a source terminal selectively coupled to said second voltage supply line via said blocking transistor, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch.

4. The bit storage circuit of claim 1 , further comprising a pixel electrode coupled to said output of said latch.

5. The bit storage circuit of claim 1 , wherein said bit storage circuit includes no more than seven transistors.

6. The bit storage circuit of claim 1 , further comprising a pulse generator having an output coupled to said control terminal of said blocking transistor.

7. The bit storage circuit of claim 1 , wherein said control terminal of said blocking transistor is coupled to a third voltage supply line having a constant voltage between a voltage of said first voltage supply line and a voltage of said second voltage supply line, whereby said second control signal is said constant voltage, and said blocking transistor is maintained in a partially conducting state.

8. A display comprising:

a first voltage supply line;

a second voltage supply line;

an array of pixel electrodes arranged in columns and rows;

a plurality of row enable lines;

a plurality of blocking signal lines;

a plurality of bit lines; and

an array of pixel circuits arranged in columns and rows; and wherein each of said pixel circuits includes

a latch having an input coupled to one of said bit lines and an output coupled to one of said pixel electrodes;

a first switching transistor having a control terminal coupled to one of said row enable lines, said first switching transistor being operative to provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a first control signal being asserted on said row enable line;

a blocking transistor including a control terminal coupled to one of said blocking signal lines and being operative to selectively provide a conductive path and a non-conductive path between said input of said latch and said second voltage supply line responsive to a second control signal asserted on said one of said blocking signal lines; and

a plurality of column enable lines; and wherein

each pixel includes a second switching transistor having a control terminal coupled to one of said column enable lines, said second switching transistor being operative to selectively provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a third control signal being asserted on said one of said column enable lines;

said first switching transistor and said second switching transistor are coupled in series between said bit line and said input of said latch; and

each said pixel circuit is coupled to no more than one of said bit lines.

9. The display of claim 8 , wherein each of said latches includes:

a first p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;

a first n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;

a second p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch; and

a second n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal selectively coupled to said input of said latch via said blocking transistor, and a gate terminal coupled to said output of said latch.

10. The display of claim 8 , wherein each of said latches includes:

a first p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;

a first n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;

a second p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch; and

a second n-channel transistor having a source terminal selectively coupled to said second voltage supply line via said blocking transistor, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch.

11. The display of claim 8 , wherein each said pixel circuit includes no more than seven transistors.

12. A bit storage circuit in combination with a plurality of additional bit storage circuits, said bit storage circuit and said additional bit storage circuits being arranged in an array of bit storage circuits formed in and on a p-type semiconductor substrate, said bit storage circuit comprising:

a first voltage supply line;

a second voltage supply line;

a bit line;

a latch having an input and an output;

a first switching transistor having a first terminal, a second terminal, and a control terminal, said first switching transistor being operative to selectively provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a first control signal being asserted on said control terminal of said first switching transistor; and

a blocking transistor including a control terminal and being operative to selectively provide a conductive path and a non-conductive path between said input of said latch and said second voltage supply line responsive to a second control signal; and wherein each additional bit storage circuit of said array includes at least one n-well formed in said p-type substrate;

a first p-type doped region formed in said at least one n-well;

a second p-type doped region formed in said at least one n-well;

a third p-type doped region formed in said at least one n-well;

a first n-type doped region formed in said p-type substrate;

a second n-type doped region formed in said p-type substrate;

a third n-type doped region formed in said p-type substrate;

a fourth n-type doped region formed in said p-type substrate;

a fifth n-type doped region formed in said p-type substrate;

a sixth n-type doped region formed in said p-type substrate;

a seventh n-type doped region formed in said p-type substrate;

a first polysilicon gate formed over a first area of said p-type substrate disposed between said first n-type doped region and said second n-type doped region;

a second polysilicon gate formed over a second area of said p-type substrate disposed between said second n-type doped region and said third n-type doped region;

a third polysilicon gate formed over a third area of said p-type substrate disposed between said third n-type doped region and said fourth n-type doped region;

a fourth polysilicon gate formed over a fourth area of said p-type substrate disposed between said fourth n-type doped region and said fifth n-type doped region;

a fifth polysilicon gate formed over a first area of said at least one n-well disposed between said first p-type doped region and said second p-type doped region;

a sixth polysilicon gate formed over a second area of said at least one n-well disposed between said second p-type doped region and said third p-type doped region;

a seventh polysilicon gate formed over a fifth area of said p-type substrate disposed between said sixth n-type doped region and said seventh n-type doped region; and

one or more conductive layers formed over said substrate and said polysilicon gates, said one more conductive layers including

a first conductive path electrically coupling said first n-type doped region to a bit line of said array,

a second conductive path electrically coupling said first polysilicon gate to a first control line of said array,

a third conductive path electrically coupling said second polysilicon gate to a second control line of said array,

a fourth conductive path electrically coupling said third polysilicon gate to a third control line of said array,

a fifth conductive path electrically coupling said third n-typed doped region, said first p-typed doped region, said sixth polysilicon gate, and said seventh polysilicon gate,

a sixth conductive path electrically coupling said fourth polysilicon gate, said fifth polysilicon gate, said third p-type doped region, and said sixth n-type doped region,

a seventh conductive path electrically coupling said second p-type doped region to a first voltage supply line of said array, and

an eighth conductive path electrically coupling said fifth n-type doped region and said seventh n-type doped region to a second voltage supply line of said array, said second voltage supply line providing a lower voltage than said first voltage supply line.

13. The array of bit storage circuits of claim 12 , wherein said array has a pitch no greater than 3 μm.

14. The array of bit storage circuits of claim 12 , wherein:

said first control line of said array is a row enable line;

said second control line of said array is a column enable line; and

said sixth conductive path is electrically coupled to a pixel mirror.

15. The array of bit storage circuits of claim 12 , wherein each of said first n-type doped region, said second n-type doped region, and said third n-typed doped region have an area that is larger than the area of the largest one of said fourth n-typed doped region, said fifth n-typed doped region, said sixth n-typed doped region, and said seventh n-typed doped region.