Apparatus and method for wideband multi-phase clock generation
Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.
1. An inner clock generation circuit, comprising:
a selectable frequency divider, comprising:
a ring of tri-state inverters;
a reset gate on an output of each tri-state inverter in the ring; and
a reset circuit comprising one or more selectable flip-flops; and
a duty-cycle limiter that generates clock signals having a duty cycle less than 100% from three out of four quadrature clock signals.
2. The inner clock generation circuit of claim 1 , wherein the tri-state inverters are formed using complementary metal oxide semiconductor.
3. The inner clock generation circuit of claim 1 , wherein the ring comprises an injection locked frequency divider.
4. The inner clock generation circuit of claim 1 , wherein the reset gate is either a pull-up gate or a pull-down gate.
5. The inner clock generation circuit of claim 1 , wherein the reset circuit is configurable to synchronize the selectable frequency divider across channels.
6. The inner clock generation circuit of claim 1 , wherein the reset gate, the reset circuit, or a combination thereof is configured to establish a deterministic starting state of the selectable frequency divider.
7. The inner clock generation circuit of claim 1 , wherein the selectable frequency divider is selectable to divide clock signal frequency by 2, 4 or 8.
8. The inner clock generation circuit of claim 1 , wherein the selectable frequency divider is configured to generate the quadrature clock signals.
9. The inner clock generation circuit of claim 1 , wherein the duty-cycle limiter is co-located with rank 1 track and hold sampling circuits to reduce a line length for distribution of high frequency clock signals.
10. The inner clock generation circuit of claim 1 , wherein the duty-cycle limiter reduces jitter by a factor of a square root of two.
11. The inner clock generation circuit of claim 1 , wherein the duty-cycle limiter comprises a T-gate that generates a 25% duty cycle.
12. The inner clock generation circuit of claim 1 , further comprising:
a central phase-locked loop;
a clock and data recovery loop coupled to the central phase-locked loop and the selectable frequency divider;
a multiphase clock generator coupled to the selectable frequency divider;
a deskew stage coupled to the multiphase clock generator, wherein the duty-cycle limiter is coupled to the deskew stage; and
a rank 2 phase rotator coupled to the deskew stage.
13. The inner clock generation circuit of claim 12 , wherein clock signals generated by the inner clock generation circuit enable a receiver to sample data at rates from 26.5 GS/s to 160 GS/s.
14. The inner clock generation circuit of claim 12 , wherein a rank 2 track and hold circuit is coupled to the rank 2 phase rotator.
15. The inner clock generation circuit of claim 12 , wherein the clock and data recovery loop is configured to generate two phases of clock signals.
16. The inner clock generation circuit of claim 12 , wherein the multiphase clock generator and the deskew stage are configured to generate sixteen phases of clock signals.
17. A method for creating a deterministic starting state of a ring-based injection locked frequency divider in an inner clock generation circuit, comprising:
implementing a reset gate on an output of each tri-state inverter in a ring of tri-state inverters;
implementing a reset circuit comprising one or more selectable flip-flops;
applying a reset signal to each reset gate, wherein the reset gate forces the output of the tri-state inverter to a starting state; and
applying a phase select signal to the reset circuit, wherein the reset circuit inverts the output of the tri-state inverter.
18. The method of claim 17 , wherein the reset gate is implemented as either a pull-up gate or a pull-down gate.
19. The method of claim 17 , wherein the reset circuit is configurable to synchronize the ring-based injection locked frequency divider across channels.
20. An inner clock generation circuit, comprising:
a central phase-locked loop;
a clock and data recovery component coupled to the central phase-locked loop configured to generate two phases of clock signals;
a selectable frequency divider coupled to the clock and data recovery component configured to generate quadrature clock signals, comprising:
a ring of tri-state inverters;
a reset gate on an output of each tri-state inverter in the ring; and
a reset circuit comprising one or more selectable flip-flops;
a multiphase clock generator coupled to the selectable frequency divider;
a deskew stage coupled to the multiphase clock generator, wherein the multiphase clock generator and the deskew stage are configured to generate sixteen phases of clock signals;
a duty-cycle limiter coupled to the deskew stage and a rank 1 track and hold sampling circuit, wherein the duty-cycle limiter generates clock signals having a 25% duty cycle from three out of four quadrature clock signals out of the sixteen phases of clock signals; and
a rank 2 phase rotator coupled to the deskew stage and a rank 2 track and hold sampling circuit.