Split pulse width modulation to reduce crossbar array integration time
A computer-implemented method, according to one embodiment, includes: causing a multi-bit input to be split into two or more chunks, where each of the two or more chunks include at least one individual bit. Each of the two or more chunks are also converted into a respective pulse width modulated signal, and a partial result is generated in digital form for each of the respective pulse width modulated signals. Each of the partial results are scaled by a respective significance factor corresponding to each of the two or more chunks, and the scaled partial results are also accumulated.
1. A computer-implemented method, comprising:
causing a multi-bit input to be split into two or more chunks, wherein each of the two or more chunks include at least one individual bit;
causing each of the two or more chunks to be converted into a respective pulse width modulated signal;
causing a partial result to be generated in digital form for each of the respective pulse width modulated signals;
scaling each of the partial results by a respective significance factor corresponding to each of the two or more chunks; and
accumulating the scaled partial results.
2. The computer-implemented method of claim 1 , comprising:
causing the digital form of the partial results to be applied to a crossbar array of memory cells by:
causing a pulse width modulator to apply a first set of pulses to the crossbar array in a first phase, the first set of pulses corresponding to a first subset of the partial results; and
causing the pulse width modulator to apply a second set of pulses to the crossbar array in a second phase, the second set of pulses corresponding to a second subset of the partial results.
3. The computer-implemented method of claim 2 , wherein the pulses applied to the crossbar array in the first phase correspond to a higher significance than the pulses applied to the crossbar array in the second phase.
4. The computer-implemented method of claim 3 , wherein causing the pulse width modulator to apply a second set of pulses to the crossbar array in a second phase includes:
ignoring a final pulse in the second set of pulses.
5. The computer-implemented method of claim 2 , wherein the crossbar array is an analog crossbar array in resistive memory.
6. The computer-implemented method of claim 5 , wherein the resistive memory is Phase Change Memory (PCM).
7. The computer-implemented method of claim 5 , wherein the resistive memory is Resistive Random Access Memory (RRAM).
8. The computer-implemented method of claim 1 , wherein the partial results are generated in digital form by a multiply-accumulate engine.
9. The computer-implemented method of claim 1 , wherein each of the two or more chunks include two or more individual bits.
10. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a processor to cause the processor to:
cause, by the processor, a multi-bit input to be split into two or more chunks, wherein each of the two or more chunks include at least one individual bit;
cause, by the processor, each of the two or more chunks to be converted into a respective pulse width modulated signal;
cause, by the processor, a partial result to be generated in digital form for each of the respective pulse width modulated signals;
scale, by the processor, each of the partial results by a respective significance factor corresponding to each of the two or more chunks; and
accumulate, by the processor, the scaled partial results.
11. The computer program product of claim 10 , wherein the program instructions are readable and/or executable by the processor to cause the processor to:
cause, by the processor, the digital form of the partial results to be applied to a crossbar array of memory cells by:
causing a pulse width modulator to apply a first set of pulses to the crossbar array in a first phase, the first set of pulses corresponding to a first subset of the partial results; and
causing the pulse width modulator to apply a second set of pulses to the crossbar array in a second phase, the second set of pulses corresponding to a second subset of the partial results.
12. The computer program product of claim 11 , wherein the pulses applied to the crossbar array in the first phase correspond to a higher significance than the pulses applied to the crossbar array in the second phase.
13. The computer program product of claim 12 , wherein causing the pulse width modulator to apply a second set of pulses to the crossbar array in a second phase includes:
ignoring a final pulse in the second set of pulses.
14. The computer program product of claim 11 , wherein the crossbar array is an analog crossbar array in resistive memory.
15. The computer program product of claim 14 , wherein the resistive memory is Phase Change Memory (PCM).
16. The computer program product of claim 14 , wherein the resistive memory is Resistive Random Access Memory (RRAM).
17. The computer program product of claim 10 , wherein the partial results are generated in digital form by a multiply-accumulate engine.
18. A system, comprising:
a processor; and
logic integrated with the processor, executable by the processor, or integrated with and executable by the processor, the logic being configured to:
cause, by the processor, a multi-bit input to be split into two or more chunks, wherein each of the two or more chunks include at least one individual bit;
cause, by the processor, each of the two or more chunks to be converted into a respective pulse width modulated signal;
cause, by the processor, a partial result to be generated in digital form for each of the respective pulse width modulated signals;
scale, by the processor, each of the partial results by a respective significance factor corresponding to each of the two or more chunks; and
accumulate, by the processor, the scaled partial results.
19. The system of claim 18 , wherein the logic is configured to:
cause, by the processor, the digital form of the partial results to be applied to a crossbar array of memory cells by:
causing a pulse width modulator to apply a first set of pulses to the crossbar array in a first phase, the first set of pulses corresponding to a first subset of the partial results; and
causing the pulse width modulator to apply a second set of pulses to the crossbar array in a second phase, the second set of pulses corresponding to a second subset of the partial results.
20. The system of claim 19 , wherein the pulses applied to the crossbar array in the first phase correspond to a higher significance than the pulses applied to the crossbar array in the second phase, wherein causing the pulse width modulator to apply a second set of pulses to the crossbar array in a second phase includes: ignoring a final pulse in the second set of pulses.