Early lock detection for phase locked loops

1. A calibration circuit, comprising:

a first counter configured to count cycles of an output clock signal generated by a phase-locked loop (PLL);

a second counter configured to count cycles of a reference clock signal;

a comparator configured to assert a match signal when a multibit output of the first counter differs from a target value input by no more than a maximum difference; and

a controller configured to:

configure the target value input of the comparator with a first target value;

configure the second counter to count a first number of cycles of the reference clock signal;

assert an early phase lock signal when the cycles of the output clock signal counted by the first counter differs from the first target value by no more than a first maximum difference after the second counter has counted the first number of cycles;

configure the target value input of the comparator with a second target value;

configure the second counter to count a second number of cycles of the reference clock signal; and

assert a final phase lock signal when the cycles of the output clock signal counted by the first counter differs from the second target value by no more than a second maximum difference after the second counter has counted the second number of cycles,

wherein the output clock signal is used to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.

2. The calibration circuit of claim 1 , wherein the controller is further configured to:

configure the second counter to continue counting from a value corresponding to the first number after the early phase lock signal is asserted.

3. The calibration circuit of claim 1 , wherein the controller is further configured to:

configure the first counter to continue counting from a value corresponding to its output captured when the early phase lock signal is asserted.

4. The calibration circuit of claim 1 , wherein the first maximum difference has the same value as the second maximum difference.

5. The calibration circuit of claim 1 , wherein the first number of cycles of the reference clock signal corresponds to a first duration of time, and wherein the second number of cycles of the reference clock signal corresponds to a second duration of time that is greater than the first duration of time.

6. The calibration circuit of claim 5 , wherein the controller is further configured to:

cause the PLL to adjust frequency of the output clock signal when the cycles of the output clock signal counted within the first duration of time differs from the first target value by more than the first maximum difference before the early phase lock signal is asserted; and

cause the PLL to adjust frequency of the output clock signal when the cycles of the output clock signal counted within the second duration of time differ from the first target value by more than the second maximum difference after the early phase lock signal is asserted.

7. The calibration circuit of claim 1 , wherein the controller is further configured to:

configure a first bandwidth of the PLL before the early phase lock signal is asserted; and

configure a second bandwidth of the PLL after the final phase lock signal is asserted, wherein the first bandwidth is greater than the second bandwidth,

wherein bandwidth of the PLL is configured by modifying a resistance value or a capacitance value in a low pass filter within the PLL.

8. A method for calibrating a phase locked loop (PLL), comprising:

repetitively counting cycles of an output clock signal generated by the PLL until an early phase lock signal is asserted when the cycles of the output clock signal counted within a first duration of time differ from a first target value by no more than a first maximum difference;

repetitively counting cycles of the output clock signal until a final phase lock signal is asserted when the cycles of the output clock signal counted within a second duration of time differ from a second target value by no more than a second maximum difference, the second duration of time being greater than the first duration of time; and

using the output clock signal to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.

9. The method of claim 8 , further comprising:

configuring a reference counter to count a first number of cycles of a reference clock signal before the early phase lock signal is asserted, the duration of the first number of cycles of the reference clock signal corresponding to the first duration of time; and

configuring the reference counter to count a second number of cycles of the reference clock signal after the early phase lock signal is asserted, the duration of the second number of cycles of the reference clock signal corresponding to the first duration of time.

10. The method of claim 9 , further comprising:

configuring the reference counter to continue counting from a value corresponding to the first number after the early phase lock signal is asserted, wherein the second number is greater than the first number.

11. The method of claim 8 , further comprising:

configuring a PLL counter to count cycles of the output clock signal generated by the PLL;

configuring a comparator to compare an output of the PLL counter to the first target value before the early phase lock signal is asserted; and

configuring the comparator to compare an output of the PLL counter to the second target value after the early phase lock signal is asserted.

12. The method of claim 11 , further comprising:

configuring the PLL counter to continue counting from a value corresponding to its output captured when the early phase lock signal is asserted.

13. The method of claim 8 , further comprising:

causing the PLL to adjust frequency of the output clock signal when the cycles of the output clock signal counted within the first duration of time differs from the first target value by more than the first maximum difference before the early phase lock signal is asserted; and

causing the PLL to adjust frequency of the output clock signal when the cycles of the output clock signal counted within the second duration of time differ from the first target value by more than the second maximum difference after the early phase lock signal is asserted.

14. The method of claim 13 , wherein causing the PLL to adjust the frequency of the output clock signal comprises:

reconfiguring a control input provided to a charge pump within the PLL.

15. The method of claim 8 , further comprising:

configuring a first bandwidth of the PLL before the early phase lock signal is asserted; and

configuring a second bandwidth of the PLL after the final phase lock signal is asserted, wherein the first bandwidth is greater than the second bandwidth,

wherein bandwidth of the PLL is configured by modifying a resistance value or a capacitance value in a low pass filter within the PLL.

16. A processor-readable storage medium storing code thereon, the code when executed by a processor causes a calibration circuit to:

repetitively count cycles of an output clock signal generated by a phase locked loop (PLL) until an early phase lock signal is asserted when the cycles of the output clock signal counted within a first duration of time differ from a first target value by no more than a first maximum difference;

repetitively count cycles of the output clock signal until a final phase lock signal is asserted when the cycles of the output clock signal counted within a second duration of time differ from a second target value by no more than a second maximum difference, the second duration of time being greater than the first duration of time; and

use the output clock signal to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.

17. The processor-readable storage medium of claim 16 , wherein the code further causes the calibration circuit to:

configure a reference counter to count a first number of cycles of a reference clock signal before the early phase lock signal is asserted, the duration of the first number of cycles of the reference clock signal corresponding to the first duration of time; and

configure the reference counter to count a second number of cycles of the reference clock signal after the early phase lock signal is asserted, the duration of the second number of cycles of the reference clock signal corresponding to the second duration of time.

18. The processor-readable storage medium of claim 17 , wherein the code further causes the calibration circuit to:

configure the reference counter to continue counting from a value corresponding to the first number after the early phase lock signal is asserted, wherein the second number is greater than the first number.

19. The processor-readable storage medium of claim 16 , wherein the code further causes the calibration circuit to:

configure a PLL counter to count cycles of the output clock signal generated by the PLL;

configure a comparator to compare an output of the PLL counter to the first target value before the early phase lock signal is asserted;

configure the comparator to compare an output of the PLL counter to the second target value after the early phase lock signal is asserted; and

configure the PLL counter to continue counting from a value corresponding to its output captured when the early phase lock signal is asserted.

20. The processor-readable storage medium of claim 16 , wherein the code further causes the calibration circuit to:

configure a first bandwidth of the PLL before the early phase lock signal is asserted; and

configure a second bandwidth of the PLL after the final phase lock signal is asserted, wherein the first bandwidth is greater than the second bandwidth,

wherein bandwidth of the PLL is configured by modifying a resistance value or a capacitance value in a low pass filter within the PLL.