Test time reduction in circuits with redundancy flip-flops
According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N−1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N−1 number of redundant flip-flops is observed through the functional path to determine faults.
1. A digital circuit, comprising:
N number of redundant flip-flops, each of the N number of redundant flip-flops having a data input coupled to a common data signal, the digital circuit configured to operate in a functional mode corresponding to a regular operation of the digital circuit and a test mode corresponding to testing of various paths of the digital circuit,
wherein the digital circuit, during the functional mode, is configured to:
combine a functional output signal of each of the N number of redundant flip-flops using logic gates; and
provide a single functional output signal in a fault-tolerant, safety-critical system based on the combining, and
wherein the digital circuit, during the test mode, is configured to:
arrange a first flip-flop of the N number of redundant flip-flops as part of a test path;
arrange N−1 number of the N number of redundant flip-flops as shadow logic by bypassing the N−1 number of the N number of redundant flip-flops from the test path, the N number of redundant flip-flops receiving a test pattern at the common data signal;
observe a test output signal at an output terminal of the first flip-flop to determine faults within a test path comprising the first flip-flop; and
observe test output signals of each of the N−1 number of redundant flip-flops to determine faults within the N−1 number of redundant flip-flops, the test output signal at the output terminal of the first flip-flop and the test output signals of each of the N−1 number of redundant flip-flops are observed at a same test cycle.
2. The digital circuit of claim 1 , wherein the digital circuit is a triple-voting flip-flop and N equals three.
3. The digital circuit of claim 1 , wherein the digital circuit is an in-situ monitor circuit.
4. The digital circuit of claim 3 , wherein N equals two.
5. The digital circuit of claim 3 , wherein the in-situ monitor circuit is a flop-based or a latch-based flip-flop, and wherein the in-situ monitor circuit is a canary type in-situ monitor circuit used to detect timing errors in an integrated circuit.
6. The digital circuit of claim 1 , wherein the digital circuit is part of an integrated circuit in an automotive system, wherein the automotive system is an airbag, an anti-lock brake, a power steering, a headlight and brake light, a cruise control, or an autonomous driving system.
7. The digital circuit of claim 1 , wherein an operation of the N−1 number of the N number of redundant flip-flops is in accordance with a shadow logic inserted at a synthesis/gate level through a connect/disconnect script.
8. An integrated circuit comprising a digital circuit, the digital circuit comprising:
N number of redundant flip-flops, each of the N number of redundant flip-flops having a data input coupled to a common data signal, the digital circuit configured to operate in a functional mode corresponding to a regular operation of the digital circuit and a test mode corresponding to testing of various paths of the digital circuit,
wherein the digital circuit, during the functional mode, is configured to:
combine a functional output signal of each of the N number of redundant flip-flops using logic gates; and
provide a single functional output signal in a fault-tolerant, safety-critical system based on the combining, and
wherein the digital circuit, during the test mode, is configured to:
arrange a first flip-flop of the N number of redundant flip-flops as part of a test path;
arrange N−1 number of the N number of redundant flip-flops as shadow logic by bypassing the N−1 number of the N number of redundant flip-flops from the test path, the N number of redundant flip-flops receiving a test pattern at the common data signal;
observe a test output signal at an output terminal of the first flip-flop to determine faults within a test path comprising the first flip-flop; and
observe test output signals of each of the N−1 number of redundant flip-flops to determine faults within the N−1 number of redundant flip-flops, the test output signal at the output terminal of the first flip-flop and the test output signals of each of the N−1 number of redundant flip-flops are observed at a same test cycle.
9. The integrated circuit of claim 8 , wherein the digital circuit is a triple-voting flip-flop and N equals three.
10. The integrated circuit of claim 8 , wherein the digital circuit is an in-situ monitor circuit.
11. The integrated circuit of claim 10 , wherein N equals two.
12. The integrated circuit of claim 10 , wherein the in-situ monitor circuit is a flop-based or a latch-based flip-flop, and wherein the in-situ monitor circuit is a canary implementation of an in-situ monitor circuit used to detect timing errors in the integrated circuit.
13. The integrated circuit of claim 8 , wherein the integrated circuit is an integrated circuit in an automotive system, wherein the automotive system is an airbag, an anti-lock brake, a power steering, a headlight and brake light, a cruise control, or an autonomous driving system.
14. The integrated circuit of claim 8 , wherein an operation of the N−1 number of the N number of redundant flip-flops is in accordance with a shadow logic inserted at a synthesis/gate level through a connect/disconnect script.
15. A method of operating a digital circuit having N number of redundant flip-flops, each of the N number of redundant flip-flops having a data input coupled to a common data signal, the method comprising:
operating the digital circuit in a functional mode corresponding to a regular operation of the digital circuit, wherein, during the functional mode, the method comprises:
combining a functional output signal of each of the N number of redundant flip-flops using logic gates; and
providing a single functional output signal in a fault-tolerant, safety-critical system based on the combining; and
operating the digital circuit in a test mode corresponding to testing of various paths of the digital circuit, wherein, during the test mode, the method comprises:
arranging a first flip-flop of the N number of redundant flip-flops as part of a test path,
arranging N−1 number of the N number of redundant flip-flops as shadow logic by bypassing the N−1 number of the N number of redundant flip-flops from the test path, the N number of redundant flip-flops receiving a test pattern at the common data signal,
observing a test output signal at an output terminal of the first flip-flop to determine faults within a test path comprising the first flip-flop, and
observing test output signals of each of the N−1 number of redundant flip-flops to determine faults within the N−1 number of redundant flip-flops, wherein observing the test output signal at the output terminal of the first flip-flop and the test output signals of each of the N−1 number of redundant flip-flops are during a same test cycle.
16. The method of claim 15 , wherein the digital circuit is a triple-voting flip-flop and N equals three.
17. The method of claim 15 , wherein the digital circuit is an in-situ monitor circuit.
18. The method of claim 17 , wherein N equals two.
19. The method of claim 17 , wherein the in-situ monitor circuit is a flop-based or a latch-based flip-flop, and wherein the in-situ monitor circuit is a canary type in-situ monitor circuit used to detect timing errors in an integrated circuit.
20. The method of claim 15 , wherein the digital circuit is part of an integrated circuit in an automotive system, wherein the automotive system is an airbag, an anti-lock brake, a power steering, a headlight and brake light, a cruise control, or an autonomous driving system.