Granted Patent B2

US 12,282,525 · App. 18/386,771 · Granted Apr 22, 2025

Inventors: Raanan Sade (Kibutz Sarid, IL); Simon Rubanovich (Haifa, IL); Amit Gradstein (Binyamina, IL); Zeev Sperber (Zichron Yackov, IL); Alexander Heinecke (San Jose, CA); Robert Valentine (Kiryat Tivon, IL); Mark J. Charney (Lexington, MA); Bret Toll (Hillsboro, OR); Jesus Corbal (King City, OR); Elmoustapha Ould-Ahmed-Vall (Chandler, AZ); Menachem Adelman (Modi'in, IL)

Assignee: Intel Corporation

G06F17/16G06F9/30036G06F9/30038G06F9/30101

Abstract

Claims (21)

1. An apparatus comprising:

decode circuitry configured to decode at least an instance of a single instruction having an opcode and memory location information, wherein the opcode is to indicate execution circuitry is to retrieve configuration information about how storage of the apparatus was configured as two-dimensional data structures to be used by execution circuitry configured to perform two-dimensional matrix operations and store the retrieved configuration information as description data at a memory location to be identified from the memory location information, wherein the description data is to include a palette identifier, and a value to indicate a row to be used to restart; and

execution circuitry, in response to the decoded instance of the single instruction, to be configured to execute the decoded instance of the single instruction according to the opcode.

2. The apparatus of claim 1 , wherein the storage is a plurality of packed data registers and the two-dimensional data structures are overlaid on the plurality of packed data registers.

3. The apparatus of claim 1 , wherein the memory location is to be accessed using information to be stored in a scale-index-base format.

4. The apparatus of claim 1 , wherein the description data comprises an index into a table which is to store a number of bytes in a two-dimensional data structure, and bytes per row of the two-dimensional data structure and indications of a number of rows and columns per two-dimensional data structure.

5. The apparatus of claim 1 , wherein the description data is to be retrieved from at least one register of the apparatus.

6. An apparatus comprising:

a processor core comprising decode circuitry configured to decode at least an instance of a single instruction having an opcode and memory location information, wherein the opcode is to indicate execution circuitry is to retrieve configuration information about how storage of the apparatus was configured as two-dimensional data structures to be used by execution circuitry configured to perform two-dimensional matrix operations and store the retrieved configuration information as description data at a memory location to be identified from the memory location information, wherein the description data is to include a palette identifier, and a value to indicate a row to be used to restart; and

an accelerator comprising execution circuitry, in response to the decoded instance of the single instruction, to be configured to execute the decoded instance of the single instruction according to the opcode.

7. The apparatus of claim 6 , wherein the storage is a plurality of packed data registers and the two-dimensional data structures are overlaid on the plurality of packed data registers.

8. The apparatus of claim 6 , wherein the memory location is to be accessed using information to be stored in a scale-index-base format.

9. The apparatus of claim 6 , wherein the description data comprises an index into a table which is to store a number of bytes in a two-dimensional data structure, and bytes per row of the two-dimensional data structure and indications of a number of rows and columns per two-dimensional data structure.

10. The apparatus of claim 6 , wherein the description data is to be retrieved from at least one register of the apparatus.

11. A non-transitory machine readable medium storing an occurrence of an instruction, wherein a processor upon encountering the occurrence of the instruction is to perform a method comprising:

decoding at least an instance of a single instruction having an opcode and memory location information, wherein the opcode is to indicate execution circuitry is to retrieve configuration information about how storage of an apparatus was configured as two-dimensional data structures to be used by execution circuitry configured to perform two-dimensional matrix operations and store the retrieved configuration information as description data at a memory location to be identified from the memory location information, wherein the description data is to include a palette identifier, and a value to indicate a row to be used to restart; and

executing the decoded instance of the single instruction to retrieve configuration information about how storage of an apparatus was configured as two-dimensional data structures to be used by execution circuitry configured to perform two-dimensional matrix operations and store the retrieved configuration information as description data at a memory location identified from the memory location information.

12. The non-transitory machine readable medium of claim 11 , wherein the storage is a plurality of packed data registers and the two-dimensional data structures are overlaid on the plurality of packed data registers.

13. The non-transitory machine readable medium of claim 11 , wherein the memory location is accessed using information to be stored in a scale-index-base format.

14. The non-transitory machine readable medium of claim 11 , wherein the description data comprises an index into a table which is to store a number of bytes in a two-dimensional data structure, and bytes per row of the two-dimensional data structure and indications of a number of rows and columns per two-dimensional data structure.

15. The non-transitory machine readable medium of claim 11 , wherein the description data is to be retrieved from at least one register.

Continuity (2)

References Cited (197)