Ferroelectric or paraelectric based low power multiplier array
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.
1. An apparatus comprising:
a plurality of multiplier inputs;
a plurality of multiplicand inputs; and
a plurality of multiplier cells organized in an array, wherein an individual multiplier cell of the plurality of multiplier cells includes:
an AND gate that receives a multiplier input from the plurality of multiplier inputs, and a multiplicand input from the plurality of multiplicand inputs; and
a 1-bit full adder coupled to the AND gate, wherein the 1-bit full adder comprises a majority or a minority gate, and wherein the 1-bit full adder comprises non-linear polar material, wherein the AND gate comprises:
a first capacitor to receive the multiplier input, the first capacitor coupled to a node;
a second capacitor to receive the multiplicand input, the second capacitor coupled to the node; and
a third capacitor coupled to a ground node, wherein the third capacitor is coupled to the node, wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material.
2. The apparatus of claim 1 , wherein a carry out of a first multiplier cell of a first row of the array, is provided as a carry-in input to a first multiplier cell of a second row of the array.
3. The apparatus of claim 2 , wherein a sum output of a second multiplier cell of the first row of the array, is provided as a sum input to the first multiplier cell of the second row of the array.
4. The apparatus of claim 2 , wherein a last row of the array comprises a plurality of 1-bit adders that receive one or more inputs from a second to last row of multiplier cells from the plurality of multiplier cells.
5. The apparatus of claim 1 , wherein the AND gate comprises a majority or minority gate.
6. The apparatus of claim 5 , wherein the individual multiplier cell comprises a buffer coupled to an output of the AND gate.
7. The apparatus of claim 5 , wherein the 1-bit full adder is to:
receive a sum input as a first input;
receive a first output from the AND gate as a second input;
receive a carry-in input as a third input;
generate a carry-out output; and
generate a sum output.
8. The apparatus of claim 7 , wherein the 1-bit full adder comprises:
a 3-input majority gate to receive the first input, the second input, and the third input, wherein the 3-input majority gate is to generate a second output which is a first majority function of the first input, the second input, and the third input;
a first inverter coupled to the second output;
a second inverter coupled to a third output of the first inverter, wherein a fourth output of the second inverter is to provide the carry-out output; and
a 5-input majority gate to receive the third output, the first input, the second input, the third input, wherein the 5-input majority gate is to generate a fifth output which is second majority function of two times the third output, and one times the first input, the second input, and the third input.
9. The apparatus of claim 8 comprises a second buffer coupled to the fifth output, wherein the second buffer is to generate a sixth output which is to drive the sum output.
10. The apparatus of claim 9 , wherein the first inverter is a first CMOS inverter, wherein the second inverter is a second CMOS inverter, and wherein the second buffer is a second CMOS buffer.
11. The apparatus of claim 8 , wherein the AND gate comprises:
a first capacitor to receive the multiplier input, the first capacitor coupled to a node;
a second capacitor to receive the multiplicand input, the second capacitor coupled to the node; and
a third capacitor coupled to a ground node, wherein the third capacitor is coupled to the node, and wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material.
12. The apparatus of claim 11 , wherein the first capacitor, the second capacitor, and the third capacitor have equal capacitances, wherein the 3-input majority gate includes three capacitors, wherein the 5-input majority gate includes five capacitors, wherein an individual capacitor of the three capacitors of the 3-input majority gate, and wherein an individual capacitor of the five capacitors of the 5-input majority gate have a same capacitance as one of the first capacitor, the second capacitor, or the third capacitor.
13. The apparatus of claim 1 , wherein the non-linear polar material includes one of:
a ferroelectric material, a paraelectric material, or a non-linear dielectric.
14. The apparatus of claim 12 , wherein the ferroelectric material includes one of:
bismuth ferrite (BFO) or BFO with a first doping material, wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
a hexagonal ferroelectric which includes one of: YMnO 3 , or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides as Hf (1-x) E x O y , where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein x and y are first and second fractions, respectively;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, wherein x and y are third and fourth fractions, respectively;
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100.
15. The apparatus of claim 13 , wherein the paraelectric material includes one of: SrTiO 3 , Ba (x) Sr (y) TiO 3 (wherein x is −0.05, and y is 0.95), HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or PMN-PT based relaxor ferroelectrics.
16. An apparatus comprising:
a plurality of multiplier inputs;
a plurality of multiplicand inputs; and
a plurality of multiplier cells organized in an array, wherein an individual multiplier cell of the plurality of multiplier cells includes:
an AND gate that receives a multiplier input from the plurality of multiplier inputs, and a multiplicand input from the plurality of multiplicand inputs, wherein the AND gate comprises a first capacitor, a second capacitor, and a third capacitor, wherein the first capacitor, the second capacitor, and the third capacitor have equal capacitances which is a first capacitance; and
a 1-bit full adder coupled to the AND gate, wherein the 1-bit full adder comprises a majority or a minority gate, wherein the 1-bit full adder comprises non-linear polar material, wherein the 1-bit full adder comprises eight capacitors, wherein an individual capacitor of the eight capacitors has a second capacitance, and wherein the first capacitance is larger than the second capacitance.
17. The apparatus of claim 16 , wherein the AND gate comprises a majority or minority gate, and wherein the 1-bit full adder is to:
receive a sum input as a first input;
receive a first output of the AND gate as a second input;
receive a carry-in input as a third input;
generate a carry-out output; and
generate a sum output.
18. The apparatus of claim 17 , wherein the 1-bit full adder comprises:
a 3-input majority gate to receive the first input, the second input, and the third input, wherein the 3-input majority gate is to generate a second output which is a first majority function of the first input, the second input, and the third input;
a first inverter coupled to the second output;
a second inverter coupled to a third output of the first inverter, wherein a fourth output of the second inverter is to provide the carry-out output; and
a 5-input majority gate to receive the third output, the first input, the second input, the third input, wherein the 5-input majority gate is to generate a fifth output which is a second majority function of two times the third output, and one times the first input, the second input, and the third input.
19. A system comprising:
a processor circuitry to execute one or more instructions;
a memory circuitry coupled to the processor circuitry, wherein the memory circuitry is to store the one or more instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes a multiplier which comprises:
a plurality of multiplier inputs;
a plurality of multiplicand inputs; and
a plurality of multiplier cells organized in an array, wherein an individual multiplier cell of the plurality of multiplier cells includes:
an AND gate that receives a multiplier input from the plurality of multiplier inputs, and a multiplicand input from the plurality of multiplicand inputs; and
a 1-bit full adder coupled to the AND gate, wherein the 1-bit full adder comprises a majority or a minority gate, and wherein the 1-bit full adder comprises non-linear polar material.
20. The system of claim 18 , wherein the non-linear polar material includes one of:
a ferroelectric material, a paraelectric material, or a non-linear dielectric.