Device with metal field plate extension
The present disclosure relates to semiconductor structures and, more particularly, to devices with a metal field plate extension and methods of manufacture. The structure includes: a gate structure over a semiconductor substrate; a drift region under the gate structure; a source region adjacent to the gate structure; a drain region in the drift region; a isolation structure within the drift region; and a contact extending from the source region and into the isolation structure within the drift region.
1. A structure comprising:
a gate structure over a semiconductor substrate;
a drift region under the gate structure;
a source region adjacent to the gate structure;
a drain region in the drift region;
an isolation structure within the drift region;
an insulator layer lining the isolation structure;
interlevel dielectric material over the insulator layer; and
a contact extending from the source region and into the isolation structure within the drift region,
wherein the contact comprises a first via interconnect structure electrically connecting to the source region, a metal field plate extension electrically connecting to the first via interconnect structure and extending partly over the drift region, and a second via interconnect structure electrically connecting to the metal field plate extension, wherein the second via interconnect structure extends into the isolation structure below the insulator layer.
2. The structure of claim 1 , wherein the gate structure partially extends over the isolation structure.
3. The structure of claim 1 , wherein the contact comprises a metal field plate extension over the drift region and the isolation structure.
4. The structure of claim 1 , wherein the isolation structure comprises a shallow trench isolation structure, and further comprising an insulator layer over the shallow trench isolation structure.
5. The structure of claim 4 , wherein the second via interconnect structure extends into the shallow trench isolation structure below the insulator layer.
6. The structure of claim 5 , wherein the shallow trench isolation structure comprises a trench filled with the interlevel dielectric material and lined with the insulator layer, and the second via interconnect structure further extends into the trench and under the insulator layer.
7. The structure of claim 1 , wherein the isolation structure comprises a local oxidation.
8. The structure of claim 7 , further comprising a trench within the local oxidation.
9. The structure of claim 7 , wherein the contact comprises a first via interconnect structure electrically connecting to the source region, a metal field plate extension electrically connecting to the first via interconnect structure and extending partly over the drift region, and a second via interconnect structure electrically connecting to the metal field plate extension, wherein the second via interconnect structure extends into the local thermal oxidation.
10. The structure of claim 1 , wherein the contact comprises a first via interconnect structure electrically connecting to the source region, a metal field plate extension electrically connecting to the first interconnect and a plurality of second via interconnect structures electrically connecting to the metal field plate extension and extending into the isolation structure.
11. The structure of claim 1 , wherein the gate structure comprises a laterally diffused metal oxide semiconductor (LDMOS) device.
12. A structure comprising:
a semiconductor substrate;
a drift region in the semiconductor substrate;
a gate structure at least partly overlapping with the drift region;
an isolation structure within the drift region and adjacent to the gate structure;
a source region and a drain region adjacent to the gate structure;
a contact electrically connected to the source region, extending over the gate structure and extending to within the isolation structure within the drift region; and
a trench within the isolation structure, the trench being lined with an insulator material and filled with an interlevel dielectric material.
13. The structure of claim 12 , wherein the contact comprises a via interconnect structure contacting the source region, a metal field plate extending over the gate structure and at least another via interconnect structure extending from the metal field plate and into the isolation structure.
14. The structure of claim 13 , wherein the at least another via interconnect structure comprises a plurality of via interconnect structures.
15. The structure of claim 12 , wherein the isolation structure comprises a shallow trench isolation structure.
16. The structure of claim 12 , wherein at least another via interconnect structure extends into the trench and underneath the insulator material.
17. The structure of claim 15 , wherein the shallow trench isolation structure extends at least partially under the gate structure.
18. The structure of claim 12 , wherein the isolation structure comprises a local oxidation.
19. A method comprising:
forming a gate structure over a semiconductor substrate;
forming a drift region under the gate structure;
forming a source region adjacent to the gate structure;
forming a drain region in the drift region;
forming an isolation structure within the drift region;
forming a contact extending from the source region and into the isolation structure within the drift region; and
forming a trench within the isolation structure, the trench being lined with an insulator material and filled with an interlevel dielectric material.