Systems and methods to store a tile register pair to memory
Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.
1. An apparatus comprising:
circuitry to receive an instruction, the instruction to identify a first two-dimensional source tile that is to be stored in memory and a second two-dimensional source tile that is to be stored in the memory; and
execution circuitry to perform operations corresponding to the instruction, including to:
determine that an indicator indicates that a pair of matrices are to be loaded; and
load elements from element positions of each row of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and load elements from element positions of each row of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile, in response to the determination that the indicator indicates that the pair of matrices are to be loaded, wherein the execution circuitry is to load every element of the first two-dimensional source tile into the first two-dimensional destination tile, and load every element of the second two-dimensional source tile into the second two-dimensional destination tile.
2. The apparatus of claim 1 , wherein the first two-dimensional source tile and the second two-dimensional source tile are to be next to one another in memory.
3. The apparatus of claim 1 , wherein the first and second two-dimensional destination tiles each comprise a plurality of registers of a processor, and wherein the execution circuitry is in a graphics processing unit.
4. The apparatus of claim 1 , wherein the first and second two-dimensional source tiles each have eight rows, and wherein the instruction has a field to specify a size of the elements of the first two-dimensional source tile.
5. The apparatus of claim 1 , further comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers; and
a processor core coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor core including the execution circuitry.
6. The apparatus of claim 1 , wherein the circuitry to receive the instruction is to convert the instruction into one or more other instructions.
7. An apparatus comprising:
circuitry to convert a first instruction into one or more other instructions, the first instruction to identify a first two-dimensional source tile that is to be stored in memory and a second two-dimensional source tile that is to be stored in the memory;
execution circuitry to perform operations corresponding to the first instruction, including to:
determine that an indicator indicates that a pair of matrices are to be loaded; and
load elements from element positions of each row of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and load elements from element positions of each row of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile, in response to the determination that the indicator indicates that the pair of matrices are to be loaded;
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers; and
a processor core coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor core including the execution circuitry.
8. The apparatus of claim 7 , wherein the execution circuitry is in a graphics processing unit.
9. The apparatus of claim 8 , wherein the first and second two-dimensional destination tiles each comprise a plurality of processor registers.
10. The apparatus of claim 9 , wherein the execution circuitry is to load every element of the first two-dimensional source tile into the first two-dimensional destination tile, and load every element of the second two-dimensional source tile into the second two-dimensional destination tile.
11. The apparatus of claim 9 , wherein the first two-dimensional source tile and the second two-dimensional source tile are to be next to one another in memory.
12. The apparatus of claim 9 , wherein the first and second two-dimensional source tiles each have eight rows, and wherein the first instruction has a field to specify a size of the elements of the first two-dimensional source tile.
13. An apparatus comprising:
an instruction converter to convert a first instruction into one or more other instructions, the first instruction identifying a first two-dimensional source tile in memory and a second two-dimensional source tile in the memory, wherein the first instruction has a field to specify a size of the elements of the first two-dimensional source tile; and
execution circuitry to perform operations corresponding to the first instruction, including to:
determine that an indicator indicates that a pair of matrices are to be loaded; and
load elements from element positions of each row of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and load elements from element positions of each row of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile, in response to the determination that the indicator indicates that the pair of matrices are to be loaded.
14. The apparatus of claim 13 , wherein the first and second two-dimensional source tiles each have eight rows.
15. The apparatus of claim 14 , wherein the execution circuitry is in a graphics processing unit.
16. The apparatus of claim 13 , wherein the first and second two-dimensional destination tiles each comprise a plurality of processor registers.
17. The apparatus of claim 13 , wherein the execution circuitry is to load every element of the first two-dimensional source tile into the first two-dimensional destination tile, and load every element of the second two-dimensional source tile into the second two-dimensional destination tile.
18. The apparatus of claim 13 , wherein the first two-dimensional source tile and the second two-dimensional source tile are to be next to one another in memory.
19. The apparatus of claim 13 , further comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers; and
a processor core coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor core including the execution circuitry.
20. The apparatus of claim 13 , wherein the instruction converter comprises a machine-readable storage medium storing instructions that when executed by the apparatus cause the apparatus to said convert the first instruction into the one or more other instructions.
21. The apparatus of claim 13 , wherein the instruction converter comprises a circuitry to convert the first instruction into the one or more other instructions.