Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts
Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.
1. A method comprising:
identifying a nested loop in a set of instructions;
configuring a first initiation interval of a first processing element of a set of interconnected processing elements to a first value and a second initiation interval of a second processing element of the set of interconnected processing elements to a second value, the second value a multiple of the first value, the first and second initiation intervals specifying a number of consecutive instructions allowed within a processing pipeline of each respective processing element;
assigning instructions of an inner loop of the nested loop to the first processing element and instructions of an outer loop of the nested loop to the second processing element; and
causing execution of the set of instructions by the first and second processing elements, the causing execution comprising encoding an indication of the configured first initiation interval and second initiation interval and the assignment of instructions into machine code representing the set of instructions or into metadata included along with the machine code.
2. The method of claim 1 , wherein the set of interconnected processing elements is a coarse grained reconfigurable array (CGRA) of a compute-near-memory system comprising a hybrid threading fabric (HTF).
3. The method of claim 1 , wherein assigning instructions of the inner loop comprises assigning at least one same instruction to at least two instruction slots of the first processing element.
4. The method of claim 3 , wherein the at least two instruction slots are selected based on an instruction slot of a preceding instruction in the nested loop and the multiple of the second value over the first value.
5. The method of claim 1 , wherein determining the first initiation interval and the second initiation interval is based on a number of instructions in the inner loop and outer loop and a number of processing elements.
6. The method of claim 1 , wherein causing execution of the instructions comprises configuring the first and second processing elements, loading the instructions according to the assignments, and initiating execution by a dispatch interface.
7. The method of claim 1 , wherein the first processing element is assigned instructions of the inner loop that are executed at a higher frequency than instructions of the outer loop assigned to the second processing element.
8. A non-transitory machine-readable medium, storing instructions, which when executed by a machine, cause the machine to perform operations comprising:
identifying a nested loop in a set of instructions;
configuring a first initiation interval of a first processing element of a set of interconnected processing elements to a first value and a second initiation interval of a second processing element of the set of interconnected processing elements to a second value, the second value a multiple of the first value, the first and second initiation intervals specifying a number of consecutive instructions allowed within a processing pipeline of each respective processing element;
assigning instructions of an inner loop of the nested loop to the first processing element and instructions of an outer loop of the nested loop to the second processing element; and
causing execution of the set of instructions by the first and second processing elements, the causing execution comprising encoding an indication of the configured first initiation interval and second initiation interval and the assignment of instructions into machine code representing the set of instructions or into metadata included along with the machine code.
9. The non-transitory machine-readable medium of claim 8 , wherein the set of interconnected processing elements is a coarse grained reconfigurable array (CGRA) of a compute-near-memory system comprising a hybrid threading fabric (HTF).
10. The non-transitory machine-readable medium of claim 8 , wherein the operations of assigning instructions of the inner loop further comprise assigning at least one same instruction to at least two instruction slots of the first processing element.
11. The non-transitory machine-readable medium of claim 10 , wherein the at least two instruction slots are selected based on an instruction slot of a preceding instruction in the nested loop and the multiple of the second value over the first value.
12. The non-transitory machine-readable medium of claim 8 , wherein the operations further comprise determining the first initiation interval and the second initiation interval is based on a number of instructions in the inner loop and outer loop and a number of processing elements.
13. The non-transitory machine-readable medium of claim 8 , wherein the operations of causing execution of the instructions further comprise configuring the first and second processing elements, loading the instructions according to the assignments, and initiating execution by a dispatch interface.
14. The non-transitory machine-readable medium of claim 8 , wherein the first processing element is assigned instructions of the inner loop that are executed at a higher frequency than instructions of the outer loop assigned to the second processing element.
15. A computing device comprising:
a processor;
a memory, storing instructions which when performed by the processor, cause the processor to perform operations comprising:
identifying a nested loop in a set of instructions;
configuring a first initiation interval of a first processing element of a set of interconnected processing elements to a first value and a second initiation interval of a second processing element of the set of interconnected processing elements to a second value, the second value a multiple of the first value, the first and second initiation intervals specifying a number of consecutive instructions allowed within a processing pipeline of each respective processing element;
assigning instructions of an inner loop of the nested loop to the first processing element and instructions of an outer loop of the nested loop to the second processing element; and
causing execution of the set of instructions by the first and second processing elements, the causing execution comprising encoding an indication of the configured first initiation interval and second initiation interval and the assignment of instructions into machine code representing the set of instructions or into metadata included along with the machine code.
16. The computing device of claim 15 , wherein the set of interconnected processing elements is a coarse grained reconfigurable array (CGRA) of a compute-near-memory system comprising a hybrid threading fabric (HTF).
17. The computing device of claim 15 , wherein the operations of assigning instructions of the inner loop further comprise assigning at least one same instruction to at least two instruction slots of the first processing element.
18. The computing device of claim 17 , wherein the at least two instruction slots are selected based on an instruction slot of a preceding instruction in the nested loop and the multiple of the second value over the first value.
19. The computing device of claim 15 , wherein the operations further comprise determining the first initiation interval and the second initiation interval is based on a number of instructions in the inner loop and outer loop and a number of processing elements.
20. The computing device of claim 15 , wherein the operations of causing execution of the instructions further comprise configuring the first and second processing elements, loading the instructions according to the assignments, and initiating execution by a dispatch interface.