Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm

1. A method for configuring a reduced instruction set computer (RISC) processor architecture to execute a fully homomorphic encryption (FHE) logic gate as a streaming topology, wherein the RISC processor architecture includes a plurality of primary processing cores defined by RISC processors, each primary processing core comprising a main memory, at least one cache memory, and a plurality of arithmetic logic units, each primary processing core having an associated node wrapper, the associated node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each arithmetic logic unit, the method comprising:

parsing sequential FHE logic gate code;

transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions;

creating the associated node wrapper around each code module; and

configuring at least one of the primary processing cores to implement a logic element equivalent of each element in a manner which operates in a streaming mode wherein data streams out of the corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

2. The method of claim 1 , wherein the transforming comprises:

locating a pointer in the FHE logic gate code;

backtracking through the FHE logic gate code to find data that was created and an allocated block of data that is pointed to by the pointer;

determining a size of the allocated block;

replacing the pointer with a data array corresponding to the allocated block; and

using the data array as streaming data.

3. A computer processor architecture for executing a fully homomorphic encryption (FHE) logic gate as a streaming topology, the computer processor architecture comprising:

a plurality of primary processing cores defined by reduced instruction set computer (RISC) processors, each primary processing core comprising a main memory, at least one cache memory, and a plurality of arithmetic logic units, each primary core having an associated node wrapper, the associated node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each of the arithmetic logic units;

wherein sequential FHE logic gate code has been transformed into a set of code modules that each have an input and an output that is a function of the input and which do not pass control to other functions, the associated node wrapper has been created around each code module; and

wherein at least one of the primary processing cores has been configured architecture to implement a logic element equivalent of each element in a manner which operates in a streaming mode wherein data streams out of the corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

4. The computer processor architecture of claim 3 , wherein the FHE logic gate code was transformed by locating a pointer in the FHE logic gate code, backtracking through the FHE logic gate code to find data that was created and an allocated block of data that is pointed to by the pointer, determining a size of the allocated block, replacing the pointer with a data array corresponding to the allocated block, and using the data array as streaming data.