IP Library Granted Patent US 12,294,167
Granted Patent B2
US 12,294,167 · App. 17/375,558 · Granted May 6, 2025

Closed loop compressed connector pin

Inventors: Xiang Li (Portland, OR); Konika Ganguly (Portland, OR); George Vergis (Portland, OR)
Assignee: Intel Corporation
H01R12/714H01R12/7076
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Quick Facts
Patent No.
US 12,294,167
App. No.
17/375,558
Granted
May 6, 2025
Kind
B2
Abstract

A connector includes connector pins that have a loop of conductor. The connector connects a first printed circuit board (PCB) to a second PCB with compression of the connector pins between the two boards. In response to compression of the connector, the connector pins make electrical contact with themselves through the loop, while also connecting pads of the first PCB to pads of the second PCB.

Claims (25)

1. A board-to-board connector, comprising:

a housing; and

connector pins to connect contacts of a first printed circuit board (PCB) to a second PCB, wherein a connector pin has a first conductor portion and a second conductor portion that form a loop, wherein, when uncompressed, the loop comprises a closed loop, wherein in response to compression of the connector, the first conductor portion is to make electrical contact with the second conductor portion, wherein the first conductor portion is to slide vertically along the second conductor portion to make a smaller closed loop in response to the compression of the connector.

2. The connector of claim 1 , wherein the connector pins pass through the housing, with a top of the loop extending through a top of the housing and a bottom of the loop extending through a bottom of the housing.

3. The connector of claim 1 , wherein the connector pins have a connector pinout with alternating ground and signal pins.

4. The connector of claim 1 , wherein the first PCB comprises a system board and the second PCB comprises a memory module.

5. The connector of claim 4 , wherein the second PCB comprises a small outline dual inline memory module (SODIMM).

6. The connector of claim 4 , wherein the memory module includes multiple dynamic random access memory (DRAM) devices.

7. The connector of claim 6 , wherein the DRAM devices comprise DRAM device compatible with a double data rate version 5 (DDR5) standard.

8. A computer system comprising:

a system board including a processor;

a memory module including multiple memory devices;

a connector to interconnect the system board to the memory module, the connector including:

a housing; and

connector pins to connect contacts of the system board to the memory module, wherein a connector pin has a first conductor portion and a second conductor portion that form a loop, wherein, when uncompressed, the loop comprises a closed loop, wherein in response to compression of the connector, the first conductor portion is to make electrical contact with the second conductor portion, wherein the first conductor portion is to slide vertically along the second conductor portion to make a smaller closed loop in response to the compression of the connector.

9. The computer system of claim 8 , wherein the connector pins pass through the housing, with a top of the loop extending through a top of the housing and a bottom of the loop extending through a bottom of the housing.

10. The computer system of claim 8 , wherein the connector pins have a connector pinout with alternating ground and signal pins.

11. The computer system of claim 8 , wherein the memory module comprises a small outline dual inline memory module (SODIMM).

12. The computer system of claim 11 , wherein the memory module includes multiple dynamic random access memory (DRAM) devices.

13. The computer system of claim 12 , wherein the DRAM devices comprise DRAM device compatible with a double data rate version 5 (DDR5) standard.

14. The computer system of claim 8 , wherein one or more of:

the processor comprises a multicore processor;

the system further includes a display communicatively coupled to a host processor of the system board;

the system further includes a network interface communicatively coupled to a host processor of the system board; or

the system further includes a battery to power the computer system.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2021
From: LI, XIANG; GANGULY, KONIKA; VERGIS, GEORGE
To: INTEL CORPORATION
Reel/Frame 056866/0965 →
Continuity (1)
Related Publication 20210344130A1 · Nov 4, 2021
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