Area optimized ferroelectric or paraelectric based low power multiplier
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.
1. An apparatus comprising:
an AND gate comprising a majority gate or a minority gate having non-linear polar material;
a buffer coupled to an output of the AND gate; and
a 1-bit full adder comprising a majority gate or a minority gate coupled to the buffer, wherein the 1-bit full adder comprises non-linear polar material.
2. The apparatus of claim 1 , wherein the 1-bit full adder is to:
receive a sum-in input as a first input;
receive a first output of the buffer as a second input;
receive a carry-in input as a third input;
generate a carry-out output; and
generate a sum output.
3. The apparatus of claim 2 , wherein the 1-bit full adder comprises:
a 3-input majority gate to receive the first input, the second input, and the third input, wherein the 3-input majority gate is to generate a second output which is a majority function of the first input, the second input, and the third input;
a first inverter coupled to the second output;
a second inverter coupled to a third output of the first inverter, wherein a fourth output of the second inverter is to provide the carry-out output; and
a 5-input majority gate to receive the third output, the first input, the second input, the third input, wherein the 5-input majority gate is to generate a fifth output which is majority function of two times the third output, and one times the first input, the second input, and the third input.
4. The apparatus of claim 3 , wherein the buffer is a first buffer, wherein the apparatus comprises a second buffer coupled to the fifth output, and wherein the buffer is to generate a sixth output which is to drive the sum output.
5. The apparatus of claim 4 , wherein the first buffer is a first CMOS buffer, wherein the first inverter is a first CMOS inverter, wherein the second inverter is a second CMOS inverter, and wherein the second buffer is a second CMOS buffer.
6. The apparatus of claim 3 , wherein the AND gate is to receive a multiplier and a multiplicand.
7. The apparatus of claim 6 , wherein the AND gate comprises:
a first capacitor to receive the multiplier, the first capacitor coupled to a node, wherein the node is coupled to the buffer;
a second capacitor to receive the multiplicand, the second capacitor coupled to the node; and
a third capacitor coupled to a ground node, wherein the third capacitor is coupled to the node, wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material.
8. The apparatus of claim 7 , wherein the first capacitor, the second capacitor, and the third capacitor have equal capacitances, wherein the 3-input majority gate includes three capacitors, wherein the 5-input majority gate includes five capacitors, wherein an individual capacitor of the three capacitors of the 3-input majority gate, and wherein an individual capacitor of the five capacitors of the 5-input majority gate have a same capacitance as one of the first capacitor, the second capacitor, or the third capacitor.
9. The apparatus of claim 1 , wherein the non-linear polar material includes one of: a ferroelectric material, a paraelectric material, or a non-linear dielectric.
10. The apparatus of claim 9 , wherein the ferroelectric material includes one of:
Bismuth ferrite (BFO) or BFO with a first doping material, wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
a hexagonal ferroelectric which includes one of: YMnO 3 , or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides such as Hf 1-x E x O y , where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein x and y are first and second fractions, respectively;
Al ( 1-x)Sc (x) N, Ga ( 1-x)Sc (x) N, Al ( 1-x)Y (x) N or Al ( 1-x-y)Mg (x) Nb (y) N, wherein x and y are third and fourth fractions, respectively;
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric which includes one of: [IPTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100.
11. The apparatus of claim 9 , wherein the paraelectric material includes: SrTiO 3 , Ba (x) Sr (y) TiO 3 (where x is −0.05, and y is 0.95), HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or PMN-PT based relaxor ferroelectrics.
12. An apparatus comprising:
an AND gate comprising a majority gate or a minority gate having non-linear polar material, wherein the AND gate comprises a first capacitor, a second capacitor, and a third capacitor, and wherein the first capacitor, the second capacitor, and the third capacitor have equal capacitances which is a first capacitance; and
a 1-bit full adder comprising a majority gate or a minority gate coupled to the AND gate, wherein the 1-bit full adder comprises non-linear polar material, wherein the 1-bit full adder comprises eight capacitors, wherein an individual capacitor of the eight capacitors has a second capacitance, and wherein the first capacitance is larger than the second capacitance.
13. The apparatus of claim 12 , wherein the 1-bit full adder is to:
receive a sum-in input as a first input;
receive a first output of the AND gate as a second input;
receive a carry-in input as a third input;
generate a carry-out output; and
generate a sum output.
14. The apparatus of claim 13 , wherein the 1-bit full adder comprises:
a 3-input majority gate to receive the first input, the second input, and the third input, wherein the 3-input majority gate is to generate a second output which is a majority function of the first input, the second input, and the third input;
a first inverter coupled to the second output;
a second inverter coupled to a third output of the first inverter, wherein a fourth output of the second inverter is to provide the carry-out output; and
a 5-input majority gate to receive the third output, the first input, the second input, the third input, wherein the 5-input majority gate is to generate a fifth output which is majority function of two times the third output, and one times the first input, the second input, and the third input.
15. The apparatus of claim 14 , comprises a buffer coupled to the fifth output, wherein the buffer is to generate a sixth output which is to drive the sum output.
16. The apparatus of claim 15 , wherein the first inverter is a first CMOS inverter, wherein the second inverter is a second CMOS inverter, and wherein the buffer is a CMOS buffer.
17. An apparatus comprising:
a first input to receive weights including an individual weight;
a second input to receive inputs including an individual input; and
a matrix multiplier coupled to the first input and the second input, wherein the matrix multiplier includes an array of multiplier cells, and wherein an individual multiplier cell of the array of multiplier cells includes:
an AND gate comprising a majority gate or a minority gate having non-linear polar material;
a buffer coupled to an output of the AND gate; and
a 1-bit full adder comprising a majority gate or a minority gate coupled to the buffer, wherein the 1-bit full adder comprises non-linear polar material.
18. The apparatus of claim 17 , wherein the AND gate comprises:
a first capacitor to receive the individual weight, the first capacitor coupled to a node;
a second capacitor to receive the individual input, the second capacitor coupled to the node; and
a third capacitor coupled to a ground node, wherein the third capacitor is coupled to the node, and wherein the first capacitor, the second capacitor, and the third capacitor include the non-linear polar material.
19. The apparatus of claim 17 , wherein the 1-bit full adder is to:
receive a sum-in input as a third input;
receive an output of the AND gate as a fourth input;
receive a carry-in input as a fifth input;
generate a carry-out output; and
generate a sum output.
20. The apparatus of claim 19 , wherein the 1-bit full adder comprises:
a 3-input majority gate to receive the third input, the fourth input, and the fifth input, wherein the 3-input majority gate is to generate a second output which is a majority function of the third input, the fourth input, and the fifth input;
a first inverter coupled to the second output;
a second inverter coupled to a third output of the first inverter, wherein a fourth output of the second inverter is to provide the carry-out output; and
a 5-input majority gate to receive the third output, the third input, the fourth input, the fifth input, wherein the 5-input majority gate is to generate a fifth output which is majority function of two times the third output, and one times the first input, the second input, and the third input.