IP Library Granted Patent US 12,298,907
Granted Patent B2
US 12,298,907 · App. 17/885,519 · Granted May 13, 2025

Systems and methods for a redundant array of independent disks (RAID) using a RAID circuit in cache coherent interconnect storage devices

Inventors: Tong Zhang (Mountain View, CA); Heekwon Park (San Jose, CA); Rekha Pitchumani (Oak Hill, VA); Yang Seok Ki (Palo Alto, CA)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F12/0828G06F3/0604G06F3/0655G06F3/0689G06F2212/621
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Quick Facts
Patent No.
US 12,298,907
App. No.
17/885,519
Granted
May 13, 2025
Kind
B2
Abstract

A system is disclosed. A first storage device may supporting a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. A second storage device may also support the cache coherent interconnect protocol. A redundant array of independent disks (RAID) circuit may communicate with the first storage device and the second storage device. The RAID circuit may apply a RAID level to the first storage device and the second storage device. The RAID circuit may be configured to receive a request using the byte level protocol and to access data on the first storage device.

Claims (20)

1. A system, comprising:

a first non-volatile storage device supporting a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol;

a second non-volatile storage device supporting the cache coherent interconnect protocol; and

a redundant array of independent disks (RAID) circuit communicating with the first non-volatile storage device and the second non-volatile storage device, the RAID circuit applying a RAID level to stripe a first data across the first non-volatile storage device and the second non-volatile storage device, the RAID circuit configured to receive a request using the byte level protocol and to access a second data on the first non-volatile storage device.

2. The system according to claim 1 , wherein the cache coherent interconnect protocol includes a Compute Express Link (CXL) protocol.

3. The system according to claim 1 , further comprising a cache coherent interconnect switch, wherein the cache coherent interconnect switch is connected to the first non-volatile storage device, the second non-volatile storage device, and the RAID circuit.

4. The system according to claim 1 , further comprising a fabric manager to configure the RAID circuit.

5. The system according to claim 4 , wherein the fabric manager is configured to identify the first non-volatile storage device and the second non-volatile storage device and configure the RAID circuit to use a RAID level.

6. The system according to claim 4 , wherein the fabric manager is configured to determine a first address range of the first non-volatile storage device and a second address range of the second non-volatile storage device and to map the first address range and the second address range to a RAID address range.

7. The system according to claim 6 , wherein the fabric manager is further configured to determine the RAID address range as accessible to a processor.

8. The system according to claim 1 , wherein the RAID circuit includes a buffer.

9. The system according to claim 8 , further comprising a backup power source configured to provide backup power to the buffer.

10. The system according to claim 1 , wherein the RAID circuit is configured to return a response based at least in part on the request.

11. The system according to claim 10 , wherein:

the request includes a load request using the byte level protocol to read the second data from the first non-volatile storage device; and

the response includes the second data.

12. The system according to claim 10 , wherein:

the request includes a store request using the byte level protocol to write the second data to the first non-volatile storage device; and

the response includes a completion response.

13. The system according to claim 8 , wherein the buffer stores a first stripe of the first data across the first non-volatile storage device and the second non-volatile storage device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2023
From: ZHANG, TONG; PARK, HEEKWON; PITCHUMANI, REKHA; KI, YANG SEOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 064796/0062 →
Continuity (2)
Provisional Application 63352629 · Jun 15, 2022
Related Publication 20230409480A1 · Dec 21, 2023
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