Method of adjusting threshold of a linear capacitive-input circuit
An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.
1. A method comprising:
during a reset phase, adjusting a threshold of a configurable logic gate by controlling a first input, a second input, and a first control, wherein the first input is coupled to a first terminal of a first capacitor, wherein a second terminal of the first capacitor is coupled to a summing node, wherein the second input is coupled to a third terminal of a second capacitor, wherein a fourth terminal of the second capacitor is coupled to the summing node, wherein the first control is coupled to a gate of a pull-up device, and wherein the pull-up device is coupled to the summing node and a power supply rail; and
during an evaluation phase after the reset phase:
turning off the pull-up device; and
evaluating an output of the configurable logic gate according to logic values on the first input and the second input.
2. The method of claim 1 , wherein the first capacitor and the second capacitor are linear capacitors.
3. The method of claim 1 comprising configuring a logic function of the configurable logic gate by adjusting the threshold.
4. The method of claim 1 comprising adjusting, in the reset phase, the threshold of the configurable logic gate to 0 by:
turning on the pull-up device;
setting the first input to logic 1; and
setting the second input to logic 0.
5. The method of claim 1 comprising adjusting, in the reset phase, the threshold of the configurable logic gate to 0 by:
turning on the pull-up device;
setting the first input to logic 0; and
setting the second input to logic 0.
6. The method of claim 1 comprising adjusting, in the reset phase, the threshold of the configurable logic gate to 1 by:
turning on the pull-up device;
setting the first input to logic 1; and
setting the second input to logic 1.
7. The method of claim 1 , wherein the first capacitor and the second capacitor include:
a linear dielectric material includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr, Y, Ta, Ba, W, Mo, or Ti; and
a top electrode and a bottom electrode, wherein the linear dielectric material is between the top electrode and the bottom electrode, and wherein the top electrode or the bottom electrode include one or more of: Cu, Al, Ag, Au, W, or Co.
8. A method comprising:
during a reset phase, adjusting a threshold of a configurable logic gate by controlling a first input, a second input, and a first control, wherein the first input is coupled to a first terminal of a first capacitor, wherein a second terminal of the first capacitor is coupled to a summing node, wherein the second input is coupled to a third terminal of a second capacitor, wherein a fourth terminal of the second capacitor is coupled to the summing node, wherein the first control is coupled to a gate of a pull-down device, and wherein the pull-down device is coupled to the summing node and a ground; and
during an evaluation phase after the reset phase:
turning off the pull-down device; and
evaluating an output of the configurable logic gate according to logic values on the first input and the second input.
9. The method of claim 8 , wherein the first capacitor and the second capacitor are linear capacitors.
10. The method of claim 8 comprising configuring a logic function of the configurable logic gate by adjusting the threshold.
11. The method of claim 8 comprising adjusting, in the reset phase, the threshold of the configurable logic gate to 2 by:
turning on the pull-down device;
setting the first input to logic 0; and
setting the second input to logic 0.
12. The method of claim 8 comprising adjusting, in the reset phase, the threshold of the configurable logic gate to 2 by:
turning on the pull-down device;
setting the first input to logic 1; and
setting the second input to logic 0.
13. The method of claim 8 comprising adjusting, in the reset phase, the threshold of the configurable logic gate to 2 by:
turning on the pull-down device;
setting the first input to logic 1; and
setting the second input to logic 1.
14. The method of claim 8 , wherein the first capacitor and the second capacitor include:
a linear dielectric material includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr, Y, Ta, Ba, W, Mo, or Ti; and
a top electrode and a bottom electrode, wherein the linear dielectric material is between the top electrode and the bottom electrode, and wherein the top electrode or the bottom electrode include one or more of: Cu, Al, Ag, Au, W, or Co.
15. A method comprising:
during a reset phase, adjusting a threshold of a configurable logic gate by controlling a first input, a second input, a first control, and a second control, wherein the first input is coupled to a first terminal of a first capacitor, wherein a second terminal of the first capacitor is coupled to a summing node, wherein the second input is coupled to a third terminal of a second capacitor, wherein a fourth terminal of the second capacitor is coupled to the summing node, wherein the first control is coupled to a gate of a pull-up device, wherein the pull-up device is coupled to the summing node and a power supply rail, wherein the second control is coupled to a gate of a pull-down device, and wherein the pull-down device is coupled to the summing node and a ground; and
during an evaluation phase after the reset phase:
turning off the pull-up device;
turning off the pull-down device; and
evaluating an output of the configurable logic gate according to logic values on the first input and the second input.
16. The method of claim 15 , wherein the first capacitor and the second capacitor include:
a linear dielectric material includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr, Y, Ta, Ba, W, Mo, or Ti; and
a top electrode and a bottom electrode, wherein the linear dielectric material is between the top electrode and the bottom electrode, and wherein the top electrode or the bottom electrode include one or more of: Cu, Al, Ag, Au, W, or Co.
17. The method of claim 15 comprising configuring a logic function of the configurable logic gate by adjusting the threshold.
18. The method of claim 15 comprising configuring a logic function of the configurable logic gate to one of, by adjusting the threshold, to an AND gate, an OR gate, or an always logic 1 gate at the summing node.
19. The method of claim 15 comprising adjusting, in the reset phase, the threshold of the configurable logic gate to 2 by:
turning on the pull-down device;
turning off the pull-up device;
setting the first input to logic 1; and
setting the second input to logic 1.
20. The method of claim 15 comprising adjusting, in the reset phase, the threshold of the configurable logic gate to 1 by:
turning on the pull-up device;
turning off the pull-down device;
setting the first input to logic 1; and
setting the second input to logic 1.