Multiplier with non-linear polar material
A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.
1. An apparatus comprising:
a first transistor positioned in a frontend of a die;
a second transistor positioned in the frontend of the die;
a first capacitor positioned above the first transistor and the second transistor;
a second capacitor positioned above the first transistor and the second transistor;
a third capacitor positioned above the first transistor and the second transistor; and
a fourth capacitor having a non-linear polar material, wherein the fourth capacitor is taller than its width, wherein the fourth capacitor is in layers above the first capacitor, the second capacitor, and the third capacitor, and wherein the first transistor and the second transistor are coupled to the fourth capacitor.
2. The apparatus of claim 1 , wherein the first capacitor has a first electrode and a second electrode, the first electrode located higher than the second electrode, wherein the apparatus comprises a first interconnect and a second interconnect, wherein the first interconnect is on the first electrode, and wherein the second electrode is on the second interconnect.
3. The apparatus of claim 2 , wherein the second capacitor has a third electrode and a fourth electrode, the third electrode located higher than the fourth electrode, wherein the apparatus comprises a third interconnect and a fourth interconnect, wherein the third interconnect is on the third electrode, and wherein the fourth electrode is on the fourth interconnect.
4. The apparatus of claim 3 , wherein the third capacitor has a fifth electrode and a sixth electrode, the fifth electrode located higher than the sixth electrode, wherein the apparatus comprises a fifth interconnect and a sixth interconnect, wherein the fifth interconnect is on the fifth electrode, and wherein the sixth electrode is on the sixth interconnect.
5. The apparatus of claim 4 comprising a seventh interconnect coupled to the second interconnect, the fourth interconnect, and the sixth interconnect.
6. The apparatus of claim 5 comprising an eighth interconnect and a ninth interconnect, wherein the fourth capacitor includes a seventh electrode and an eighth electrode, wherein the eighth interconnect is on the seventh electrode, and wherein the eighth electrode is on the ninth interconnect, wherein the ninth interconnect is coupled to the seventh interconnect, wherein the eighth interconnect is coupled to the first transistor, and wherein the ninth interconnect is coupled to the second transistor.
7. The apparatus of claim 6 , wherein the first transistor is controllable by a first control, and wherein the second transistor is controllable by a second control.
8. The apparatus of claim 6 comprising an inverter having an input coupled to the eighth interconnect.
9. The apparatus of claim 8 , wherein the inverter is a first inverter, wherein the apparatus comprises a second inverter coupled to a first output of the first inverter, wherein the first interconnect is to receive a first input, wherein the third interconnect is to receive a second input, and wherein the fifth interconnect is to receive a carry input, and wherein a second output of the second inverter is a carry output.
10. The apparatus of claim 9 comprises:
a third transistor positioned in the frontend of the die;
a fourth transistor positioned in the frontend of the die;
a fifth capacitor positioned above the third transistor and the fourth transistor;
a sixth capacitor positioned above the third transistor and the fourth transistor;
a seventh capacitor positioned above the third transistor and the fourth transistor;
an eighth capacitor positioned above the third transistor and the fourth transistor;
a ninth capacitor positioned above the third transistor and the fourth transistor; and
a tenth capacitor having the non-linear polar material, wherein the tenth capacitor is taller than its width, wherein the tenth capacitor is in layers above the fifth capacitor, the sixth capacitor, the seventh capacitor, the eighth capacitor, and the ninth capacitor, wherein the third transistor and the fourth transistor are coupled to the ninth capacitor, wherein the first output is coupled to the fourth capacitor and the fifth capacitor, wherein the first input is coupled to the seventh capacitor, wherein the second input is coupled to the eighth capacitor, and wherein the carry input is coupled to the ninth capacitor.
11. The apparatus of claim 1 , wherein the non-linear polar material comprises:
bismuth ferrite (BFO) or BFO with a first doping material, wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
a first hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
a second hexagonal ferroelectric of a type h-RMnO 3 , where R is a rare earth element including one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides of a form, Hf (1-x) Ex x O y , where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, where x and y are first and second fractions, respectively;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x )N or Al (1-x-y) Mg (x) Nb (y) N, where x and y are third and fourth fractions, respectively;
HfO 2 doped with one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric which includes one of: n or n, where ‘n’ is between 1 and 100.
12. An apparatus comprising:
a first 1-bit adder having a first input, a second input, and carry input, a sum output, and a carry output; and
an AND gate to receive a first operand and a second operand, and to generate an output which is an AND function of the first operand and the second operand, wherein the output is coupled to the second input, and wherein the first input is coupled to a sum input from a second 1-bit adder, wherein the first 1-bit adder comprises:
a first transistor positioned in a frontend of a die;
a second transistor positioned in the frontend of the die;
a first capacitor positioned above the first transistor and the second transistor;
a second capacitor positioned above the first transistor and the second transistor;
a third capacitor positioned above the first transistor and the second transistor; and
a fourth capacitor having a non-linear polar material, wherein the fourth capacitor is taller than its width, wherein the fourth capacitor is in layers above the first capacitor, the second capacitor, and the third capacitor, wherein the first transistor and the second transistor are coupled to the fourth capacitor.
13. The apparatus of claim 12 , wherein the first capacitor has a first electrode and a second electrode, the first electrode located higher than the second electrode, wherein the apparatus comprises a first interconnect and a second interconnect, wherein the first interconnect is on the first electrode, and wherein the second electrode is on the second interconnect.
14. The apparatus of claim 13 , wherein the second capacitor has a third electrode and a fourth electrode, the third electrode located higher than the fourth electrode, wherein the apparatus comprises a third interconnect and a fourth interconnect, wherein the third interconnect is on the third electrode, and wherein the fourth electrode is on the fourth interconnect.
15. The apparatus of claim 14 , wherein the third capacitor has a fifth electrode and a sixth electrode, the fifth electrode located higher than the sixth electrode, wherein the apparatus comprises a fifth interconnect and a sixth interconnect, wherein the fifth interconnect is on the fifth electrode, and wherein the sixth electrode is on the sixth interconnect.
16. The apparatus of claim 15 comprising a seventh interconnect coupled to the second interconnect, the fourth interconnect, and the sixth interconnect.
17. The apparatus of claim 16 comprising an eighth interconnect and a ninth interconnect, wherein the fourth capacitor includes a seventh electrode and an eighth electrode, wherein the eighth interconnect is on the seventh electrode, and wherein the eighth electrode is on the ninth interconnect, wherein the ninth interconnect is coupled to the seventh interconnect, wherein the eighth interconnect is coupled to the first transistor, and wherein the ninth interconnect is coupled to the second transistor.
18. The apparatus of claim 17 , wherein the first transistor is controllable by a first control, and wherein the second transistor is controllable by a second control.
19. The apparatus of claim 18 comprising an inverter having an input coupled to the eighth interconnect.
20. The apparatus of claim 19 , wherein the inverter is a first inverter, wherein the apparatus comprises a second inverter coupled to a first output of the first inverter, wherein the first interconnect is to receive the first input, wherein the third interconnect is to receive the second input, and wherein the fifth interconnect is to receive the carry input, and wherein a second output of the second inverter is the carry output.