Exclusive-or logic gate with non-linear input capacitors
A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.
1. An apparatus comprising:
a first capacitor to receive a first input, the first capacitor coupled to a node;
a second capacitor to receive a second input, the second capacitor coupled to the node;
a third capacitor to receive a third input, the third capacitor coupled to the node;
an inverter having an input coupled to the node; and
a NOR gate having an input coupled to an output of the inverter.
2. The apparatus of claim 1 , wherein the node is a first node, wherein the apparatus further comprises:
a fourth capacitor to receive the first input, the fourth capacitor coupled to a second node;
a fifth capacitor to receive the second input, the fifth capacitor coupled to the second node; and
a sixth capacitor to receive a fourth input, the sixth capacitor coupled to the second node, wherein the input of the NOR gate is a first NOR input, and wherein the NOR gate has a second NOR input coupled to the second node.
3. The apparatus of claim 2 , wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor have non-linear polar material.
4. The apparatus of claim 3 , wherein the non-linear polar material comprises:
bismuth ferrite (BFO) or BFO with a first doping material, wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
a first hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
a second hexagonal ferroelectric of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides as Hf 1-x Ex Oy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein x and y are first and second fractions, respectively;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, where x and y are third and fourth fractions, respectively;
HfO 2 doped with one of one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100.
5. The apparatus of claim 3 , wherein the non-linear polar material includes one of: a ferroelectric material, a paraelectric material, or a non-linear dielectric.
6. The apparatus of claim 5 , wherein the paraelectric material includes one of: SrTiO 3 , TiO 3 with Ba and Sr, HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or PMN-PT based relaxor ferroelectrics.
7. The apparatus of claim 5 , wherein the paraelectric material includes one of: Sr, Ti, Ba, Hf, Zr, Si, La, or Pb.
8. The apparatus of claim 2 , wherein the fourth input is a logic 0.
9. The apparatus of claim 2 , wherein leakage through the fourth capacitor, the fifth capacitor, and the sixth capacitor is configured such that a voltage is developed on the second node that reduces leakage through the NOR gate.
10. The apparatus of claim 2 , wherein the first capacitor, the second capacitor, and the third capacitor together operate as an OR gate, and wherein the fourth capacitor, the fifth capacitor, and the sixth capacitor together operate as an AND gate.
11. The apparatus of claim 2 , wherein the NOR gate is a CMOS based NOR gate.
12. The apparatus of claim 1 , wherein the third input is a logic 1.
13. The apparatus of claim 1 , wherein leakage through the first capacitor, the second capacitor, and the third capacitor is configured such that a voltage is developed on the node that reduces leakage through the inverter.
14. The apparatus of claim 1 , wherein the inverter is a CMOS based inverter.
15. An apparatus comprising:
a first set of capacitors coupled to operate as an OR gate;
a second set of capacitors coupled to operate as an AND gate;
an inverter coupled to the first set of capacitors; and
a NOR gate coupled to an output of the inverter and the second set of capacitors.
16. The apparatus of claim 15 , wherein the first set of capacitors and the second set of capacitors include non-linear polar material.
17. The apparatus of claim 15 , wherein the inverter and the NOR gate are CMOS based gates.
18. A system comprising:
a memory;
a processor coupled to the memory; and
a communication interface coupled to the processor, wherein the processor includes an XOR gate which includes:
a first set of capacitors coupled to operate as an OR gate;
a second set of capacitors coupled to operate as an AND gate;
an inverter coupled to the first set of capacitors; and
a NOR gate coupled to an output of the inverter and the second set of capacitors.
19. The system of claim 18 , wherein the first set of capacitors and the second set of capacitors include non-linear polar material.
20. The system of claim 18 , wherein the inverter and the NOR gate are CMOS based gates.