IP Library Granted Patent US 12,339,969
Granted Patent B2
US 12,339,969 · App. 18/339,017 · Granted Jun 24, 2025

System method for fractional secure boot by validating secure enclave using instructions of pre-drivers stored in memory by manufacturer

Inventors: Chirag K Shroff (Cary, NC); William F. Sulzen (Apex, NC); Ofer Licht (Scotts Valley, CA); Chandan Singh (Karnataka, IN)
Assignee: Cisco Technology, Inc.
G06F21/575G06F9/44505
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,339,969
App. No.
18/339,017
Granted
Jun 24, 2025
Kind
B2
Abstract

Disclosed are systems, apparatuses, methods, and computer-readable media for configuring network groups without software-based processing and management. A method includes: validating veracity of a secure enclave based on a secure identify of the secure enclave using the instructions of a secure enclave predriver stored in a memory integral to a processor; establishing a secure connection with the secure enclave; retrieving at least one authentication key from the secure enclave; retrieving at least a portion of a bootstrapper from a secure storage based on the instructions of the secure enclave predriver; validating a veracity of the bootstrapper based on the at least one authentication key; initializing an external memory using the instructions of the bootstrapper; copying a bootloader from the secure storage into the external memory; validating a veracity of the bootloader based on the at least one authentication key; and executing the bootloader.

Claims (44)

1. A method for securely configuring a booting operation, comprising:

validating veracity of a secure enclave based on a secure identifier of the secure enclave using instructions of a secure enclave predriver stored in a memory integral to a processor;

establishing a secure connection with the secure enclave based on the veracity of the secure enclave using the instructions of the secure enclave predriver;

retrieving at least one authentication key from the secure enclave based on the instructions of the secure enclave predriver;

retrieving at least a portion of a bootstrapper from a secure storage based on the instructions of the secure enclave predriver;

validating a veracity of the bootstrapper based on the at least one authentication key;

initializing an external memory using the instructions of the bootstrapper, wherein the external memory is connected to the processor;

copying a bootloader from the secure storage into the external memory based on the instructions in the bootstrapper or the secure enclave predriver;

validating a veracity of the bootloader based on the at least one authentication key;

clearing the at least one authentication key from the memory of the processor; and

executing the bootloader to load a least a portion of an operating system into the external memory.

2. The method of claim 1 , wherein a different processor is configured to execute the bootloader.

3. The method of claim 1 , wherein the memory comprises a first memory and a second memory.

4. The method of claim 3 , wherein the bootstrapper comprises a first portion and a second portion, and

wherein the first portion of the bootstrapper is loaded into the first memory of the processor, and the second portion of the bootstrapper is loaded in the second memory of the processor, and wherein the second portion of the bootstrapper includes instruction to initialize the external memory.

5. The method of claim 4 , wherein the at least one authentication key is loaded into a third memory of the processor.

6. The method of claim 4 , wherein the first portion of the bootstrapper is validated with a first key in the at least one authentication key and the second portion of the bootstrapper is validated with a second authentication key.

7. The method of claim 6 , wherein the second authentication key is loaded after validation of at the first portion of the bootstrapper.

8. The method of claim 4 , wherein the first portion of the bootstrapper and the second portion of the bootstrapper are loaded into the second memory of the processor, and the secure enclave predriver is loaded into the first memory of the processor.

9. The method of claim 3 , further comprising:

in response to validating the veracity of the bootstrapper, removing the secure enclave predriver from the first memory.

10. The method of claim 1 , wherein the at least one authentication key includes a first key associated with the bootstrapper and a second key associated with the bootloader is stored in a separate memory associated with a secure register.

11. A system on chip (SoC), comprising:

a processor including a memory integral to the processor and configured to execute instructions and cause the processor to:

validate veracity of a secure enclave based on a secure identifier of the secure enclave using the instructions of a secure enclave predriver stored in a memory integral to the processor;

establish a secure connection with the secure enclave based on the veracity of the secure enclave using instructions of the secure enclave predriver;

retrieve at least one authentication key from the secure enclave based on the instructions of the secure enclave predriver;

retrieve at least a portion of a bootstrapper from a secure storage based on the instructions of the secure enclave predriver;

validate a veracity of the bootstrapper based on the at least one authentication key;

initialize an external memory using the instructions of the bootstrapper, wherein the external memory is connected to the processor;

copy a bootloader from the secure storage into the external memory based on the instructions in the bootstrapper or the secure enclave predriver;

validate a veracity of the bootloader based on the at least one authentication key;

clear the at least one authentication key from the memory of the processor; and

execute the bootloader to load a least a portion of an operating system into the external memory.

12. The SoC of claim 11 , wherein a different processor is configured to execute the bootloader.

13. The SoC of claim 11 , wherein the memory comprises a first memory and a second memory.

14. The SoC of claim 13 , wherein the bootstrapper comprises a first portion and a second portion, and wherein the first portion of the bootstrapper is loaded into the first memory of the processor, and the second portion of the bootstrapper is loaded in the second memory of the processor, and wherein the second portion of the bootstrapper includes instruction to initialize the external memory.

15. The SoC of claim 14 , wherein the at least one authentication key is loaded into a third memory of the processor.

16. The SoC of claim 14 , wherein the first portion of the bootstrapper is validated with a first key in the at least one authentication key and the second portion of the bootstrapper is validated with a second authentication key.

17. The SoC of claim 16 , wherein the second authentication key is loaded after validation of at the first portion of the bootstrapper.

18. The SoC of claim 14 , wherein the first portion of the bootstrapper and the second portion of the bootstrapper are loaded into the second memory of the processor, and the secure enclave predriver is loaded into the first memory of the processor.

19. The SoC of claim 13 , wherein the processor is configured to execute the instructions and cause the processor to:

in response to validating the veracity of the bootstrapper, remove the secure enclave predriver from the first memory.

20. The SoC of claim 11 , wherein the at least one authentication key includes a first key associated with the bootstrapper and a second key associated with the bootloader is stored in a separate memory associated with a secure register.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2023
From: SHROFF, CHIRAG K; SULZEN, WILLIAM F.; LICHT, OFER; SINGH, CHANDAN
To: CISCO TECHNOLOGY, INC.
Reel/Frame 064019/0177 →
Continuity (1)
Related Publication 20240427896A1 · Dec 26, 2024
References Cited (16)
US 9246690B1 · Roth · 2016 [cited by examiner]
US 9971895B2 · Rhee · 2018 [cited by examiner]
US 11347857B2 · Fu · 2022 [cited by examiner]
US 12072982B2 · Suryanarayana · 2024 [cited by examiner]
US 20050010767A1 · Craft · 2005 [cited by examiner]
US 20090271620A1 · Sudhakar · 2009 [cited by examiner]
US 20160232356A1 · Barkelew · 2016 [cited by examiner]
US 20190007216A1 · Meriac · 2019 [cited by applicant]
US 20210312057A1 · Kloth · 2021 [cited by applicant]
US 20210406380A1 · Poulard et al. · 2021 [cited by applicant]
US 20220198018A1 · Wentz et al. · 2022 [cited by applicant]
US 20220245255A1 · Hinnershitz et al. · 2022 [cited by applicant]
US 20240419802A1 · Edwards · 2024 [cited by examiner]
Yueqiang Cheng, “Virtualization-based System Hardening against Untrusted Kernels.” pp. 1-179. Https://ink.library.smu.edu.sg/etd_coll/105 (Year: 2014). [cited by examiner]
Vincent Zimmer, “System Isolation Beyond BIOS using the Unified Extensible Firmware Interface.” Security and Management, Intel Corporation, pp. 1-7 (Year: 2008). [cited by examiner]
Apple: “Apple Platform Security”, May 2022, pp. 1-210. [cited by applicant]