Computer architecture and method for performing lattice-based cryptographic primitives with resistance to side-channel attacks
A computer processing system configured to perform lattice-based cryptographic primitives with resistance to side-channel attacks with a computer processing architecture operably configured to perform at least one of key generation, key encapsulation, and key decapsulation and process security sensitive data, a sampling submodule performing hashing operations and centered binomial sampling routines, a polynomial arithmetic unit performing polynomial multiplication, polynomial addition, and polynomial subtraction by processing the security sensitive data that is divided into shares stored on a plurality of memory banks, an auxiliary submodule mathematical operations, a data interface unit operably configured to perform input and output operations and to input data and output data in shares, and de-serialize the input data into polynomial coefficients utilized by the polynomial arithmetic unit, and a controller submodule operably configured to sequence any operations needed to perform the at least one of key generation, key encapsulation, and key decapsulation.
1. A computer processing system configured to perform lattice-based cryptographic primitives with resistance to side-channel attacks and comprising:
a computer processing architecture operably configured to perform at least one of key generation, key encapsulation, and key decapsulation and process security sensitive data;
a plurality of memory banks wherein the sensitive shares are mirrored such that control logic for memory address can be shared between memory banks and non-sensitive data is stored in a separate memory module;
a polynomial arithmetic unit communicatively coupled to the plurality of memory banks and operably configured to perform polynomial multiplication, polynomial addition, and polynomial subtraction by processing the security sensitive data that is divided into shares stored on the plurality of memory banks;
an auxiliary submodule;
communicatively coupled with a sampling submodule, wherein hardware resources include a share type converter module shared between a decoder and a decompressor;
communicatively coupled with the plurality of memory banks; and
operably configured to perform share conversion, message decoding, and ciphertext compression;
a data interface hardware unit having an interface configuration communicatively coupled to the plurality of memory banks, operably configured to perform input and output operations, operably configured to input data and output data in shares, and de-serialize the input data into polynomial coefficients operably configured to be utilized by the polynomial arithmetic unit; and
a controller submodule with a processor operably configured to sequence any operations needed to perform the at least one of key generation, key encapsulation, and key decapsulation.
2. The computer processing system according to claim 1 , wherein the sampling submodule is operably configured to perform a rejection sampling routine.
3. The computer processing system according to claim 1 , wherein the data interface unit is operably configured to de-serialize the input data into polynomial coefficients stored on the plurality of memory banks for utilization by the polynomial arithmetic unit.
4. The computer processing system according to claim 1 , wherein the sampling submodule further comprises:
a SHA3 unit; and
at least one sampling unit, wherein the SHA3 unit is operably configured to perform the hashing operations and operably configured to transfer sampling input data to the at least one sampling unit.
5. The computer processing system according to claim 4 , wherein the SHA3 unit is side-channel-resistant.
6. The computer processing system according to claim 4 , wherein the least one sampling unit further comprises:
a rejection sampling unit operably configured to generate a public uniform array and a central binomial sampling unit operably configured to convert the sampling input data to centered binomial sampling data and performs operation on masked data to provide side-channel resistance.
7. The computer processing system according to claim 1 , wherein the auxiliary submodule further comprises:
a share-type converter operably configured to perform the share conversion; form arithmetic to Boolean or from Boolean to arithmetic;
a message decoder operably configured to perform the message decoding; and
a ciphertext compressor operably configured to perform the ciphertext compression, the share-type converter, the message decoder, and the ciphertext compressor resistant to first-order side channel attacks.
8. The computer processing system according to claim 7 , wherein the message decoder and the ciphertext compressor share the share-type converter to reduce area consumption.
9. The computer processing system according to claim 1 , wherein the controller submodule further comprises:
a processor, control code, a configuration register, a selection register, and a status register, wherein the controller submodule is operably configured to alternatively sequence any of the operations needed to perform the least one of key generation, key encapsulation, and key decapsulation by only modifying the control code.
10. The computer processing system according to claim 1 , wherein the computer processing architecture is operably configured to perform at least one of CRYSTALS-Kyber, Saber, NTRU, and FrodoKEM.