Image sensor device
An image sensor device including: a first digital pixel including a first photodetector and first memory cells to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and second memory cells to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first memory cells and the second memory cells are connected with a plurality of bit lines, the first memory cells are connected with a first word line and a third word line, the second memory cells are connected with a second word line and a fourth word line, the second word line is between the first and third word lines, and the third word line is between the second and fourth word lines.
1. An image sensor device, comprising:
a first substrate including a plurality of first pixel circuits; and
a second substrate including a plurality of second pixel circuits,
wherein the plurality of first pixel circuits includes a first photo detector and a second photo detector,
wherein the plurality of second pixel circuits includes:
a first memory circuit including first memory cells configured to store a first digital signal generated from the first photo detector and first dummy memory cells; and
a second memory circuit including second memory cells configured to store a second digital signal generated from the second photo detector and second dummy memory cells,
wherein the first memory circuit is disposed directly adjacent to the second memory circuit in a first direction, and
wherein one of the plurality of first pixel circuits and one of the plurality of second pixel circuits constitute one digital pixel.
2. The image sensor device of claim 1 , wherein the first memory cells are disposed directly adjacent to the second memory cells, and
wherein the first dummy memory cells or the second dummy memory cells are not disposed between the first memory cells and the second memory cells.
3. The image sensor device of claim 1 , wherein the one of the plurality of first pixel circuits and the one of the plurality of second pixel circuits are electrically connected via Cu-to-Cu bonding.
4. The image sensor device of claim 3 , wherein the one of the plurality of first pixel circuits includes a portion of a comparator and the one of the plurality of second pixel circuits includes a remaining portion of the comparator.
5. The image sensor device of claim 1 , wherein the plurality of first pixel circuits further comprises a third photo detector,
wherein the plurality of second pixel circuits further comprises a third memory circuit, the third memory circuit including third memory cells configured to store a third digital signal generated from the third photo detector and third dummy memory cells, and
wherein the third memory circuit is disposed directly adjacent to the first memory circuit in a second direction perpendicular to the first direction.
6. The image sensor device of claim 5 , wherein the plurality of first pixel circuits further comprises a fourth photo detector,
wherein the plurality of second pixel circuits further comprises a fourth memory circuit, the fourth memory circuit including fourth memory cells configured to store a fourth digital signal generated from the fourth photo detector and fourth dummy memory cells, and
wherein the fourth memory circuit is disposed directly adjacent to the second memory circuit in the second direction.
7. The image sensor device of claim 6 , wherein the third memory circuit is disposed directly adjacent to the fourth memory circuit in the first direction, and
wherein the third dummy memory cells and the fourth dummy memory cells are not disposed between the third memory cells and the fourth memory cells.
8. The image sensor device of claim 6 , wherein the first to fourth dummy memory cells surround the first to fourth memory cells.
9. The image sensor device of claim 6 , wherein the first to fourth memory cells are connected to a plurality of bit lines and a plurality of word lines.
10. The image sensor device of claim 1 , where the second substrate further comprises:
a counter configured to output a code; and
a row driver configured to control the plurality of first pixel circuits and the plurality of second pixel circuits.
11. The image sensor device of claim 6 , wherein the first to fourth photo detectors are connected to a first portion of a comparator.
12. The image sensor device of claim 1 , further comprises a third substrate stacked on the second substrate, and
wherein the third substrate includes a digital logic circuit.
13. The image sensor device of claim 12 , wherein the second substrate and the third substrate are connected via Cu-to-Cu bonding.
14. The image sensor device of claim 12 , wherein the second substrate and the third substrate are connected via TSV.
15. An image sensor device, comprising:
a first substrate including a plurality of photo detectors; and
a second substrate including N×M memory cells for storing a plurality of digital signals generated from the plurality of photo detectors and a plurality of dummy memory cells,
wherein the N×M memory cells does not include any one of the plurality of dummy memory cells,
wherein N and M are integers greater than 1, and
wherein the first substrate is stacked on the second substrate such that the N×M memory cells overlap the plurality photo detectors.
16. The image sensor device of claim 15 , wherein the plurality of dummy memory cells are disposed along at least two sides of the N×M memory cells.
17. The image sensor device of claim 16 , wherein the plurality of dummy memory cells surround the N×M memory cells.
18. An image sensor device, comprising:
a first substrate including:
a first pixel circuit including a first photo detector, and
a second pixel circuit including a second photo detector; and
a second substrate including:
a first memory circuit including first memory cells configured to store a first digital signal generated from the first photo detector and first dummy memory cells, and
a second memory circuit including second memory cells configured to store a second digital signal generated from the second photo detector and second dummy memory cells,
wherein the first memory circuit is disposed directly adjacent to the second memory circuit in a first direction,
wherein the first substrate is stacked on the second substrate such that the first photo detector and the first memory circuit are overlapped and the second photo detector and the second memory circuit are overlapped.
19. The image sensor device of claim 18 , wherein the first substrate further comprises a third photo detector,
wherein the second substrate further comprises a third memory circuit, the third memory circuit including third memory cells configured to store a third digital signal generated from the third photo detector and third dummy memory cells, and
wherein the third memory circuit is disposed directly adjacent to the first memory circuit in a second direction perpendicular to the first direction.
20. The image sensor device of claim 19 , further comprising a third substrate stacked on the second substrate, and
wherein the third substrate includes a digital logic circuit.