Distributing matrix multiplication processing among processing nodes
View Patent ↗Based on a predetermined number of available processor sockets, a plurality of candidate matrix decompositions are identified, which correspond to a multiplication of matrices. Based on a first comparative relationship of a variation of first sizes of the plurality of candidate matrix decompositions along a first dimension and a second comparative relationship of a variation of second sizes of the plurality of candidate matrix decomposition sizes along a second dimension, a given candidate matrix decomposition is selected. Processing of the multiplication among the processor sockets is distributed based on the given candidate matrix decomposition.
1. A method comprising:
partitioning, by at least one hardware processor, matrices associated with a matrix multiplication into a plurality of partitions that corresponds to a plurality of processor sockets;
sizing, by the at least one hardware processor, the plurality of partitions based on first costs corresponding to candidate matrix decompositions to provide a plurality of sized partitions, wherein a given first cost of the first costs is based on a first comparative analysis of first block sizes of the corresponding candidate matrix decomposition along a first dimension and second block sizes of the corresponding candidate matrix decomposition along a second dimension;
assigning, by the at least one hardware processor, the plurality of sized partitions to the plurality of processor sockets, in a manner that a given set of sized partitions of the plurality of sized partitions is assigned to a given processor socket of the plurality of processor sockets;
for the given set of sized partitions, subdividing, by the at least one hardware processor, the partitions of the given set based on second costs corresponding to candidate matrix sub-decompositions to provide a plurality of sized sub-partitions, wherein a given second cost of the second costs is based on a second comparative analysis of first sub-block sizes of the corresponding candidate matrix sub-decomposition along the first dimension and second sub-block sizes of the corresponding candidate matrix sub-decomposition along the second dimension; and
assigning, by the at least one hardware processor, the plurality of sized sub-partitions to a plurality of processing nodes of the given processor socket for performing processing of the multiplication.
2. The method of claim 1 , further comprising:
based on a processing core per processing node number, identifying a plurality of candidate processing thread-to-processing core assignments;
based on at least one of a cache block size and a processor core per last level cache number, selecting a given candidate processing thread-to-processing core assignment of the plurality of candidate processing thread-to-processing core assignments; and
assign threads to each processing node of the plurality of processing nodes based on the given candidate processing thread-to-processing core assignment.
3. The method of claim 2 , further comprising processing the multiplication using a generalized matrix multiplication algorithm based on the assigned plurality of sized partitions, the plurality of sized sub-partitions and the assigned threads.
4. The method of claim 3 , wherein processing the multiplication using the generalized matrix multiplication algorithm comprises using synchronization barriers in the threads.
5. The method of claim 3 , wherein processing the multiplication using the generalized matrix multiplication algorithm comprises using node masks for memory buffers shared by the plurality of processing nodes.
6. A non-transitory storage medium that stores machine-readable instructions that, when executed by a hardware processor, cause the processor to:
partition matrices associated with a matrix multiplication into a plurality of partitions that corresponds to a plurality of processor sockets;
size the plurality of partitions based on first costs corresponding to candidate matrix decompositions to provide a plurality of sized partitions, wherein a given first cost of the first costs is based on a first comparative analysis of first block sizes of the corresponding candidate matrix decomposition along a first dimension and second block sizes of the corresponding candidate matrix decomposition along a second dimension;
assign the plurality of sized partitions to the plurality of processor sockets in a manner that a given set of sized partitions of the plurality of sized partitions is assigned to a given processor socket of the plurality of processor sockets;
for the given set of sized partitions, subdivide the partitions of the given set based on second costs corresponding to candidate matrix sub-decompositions to provide a plurality of sized sub-partitions, wherein a given second cost of the second costs is based on a second comparative analysis of first sub-block sizes of the corresponding candidate matrix sub-decomposition along the first dimension and second sub-block sizes of the corresponding candidate matrix sub-decomposition along the second dimension; and
assign the plurality of sized sub-partitions to a plurality of processing nodes of the given processor socket for performing processing of the multiplication.
7. The non-transitory storage medium of claim 6 , wherein the instructions, when executed by the hardware processor, further cause the hardware processor to:
based on a processing core per processing node number, identify a plurality of candidate processing thread-to-processing core assignments;
based on at least one of a cache block size and a processor core per last level cache number, select a given candidate processing thread-to-processing core assignment of the plurality of candidate processing thread-to-processing core assignments; and
assign threads to each processing node of the plurality of processing nodes based on the given candidate processing thread-to-processing core assignment.
8. The non-transitory storage medium of claim 7 , wherein the instructions, when executed by the hardware processor, further cause the hardware processor to:
process the multiplication using a generalized matrix multiplication algorithm based on the assigned plurality of sized partitions, the plurality of sized sub-partitions and the assigned threads.
9. The non-transitory storage medium of claim 8 , wherein processing the multiplication using the generalized matrix multiplication algorithm comprises using synchronization barriers in the threads.
10. The non-transitory storage medium of claim 8 , wherein processing the multiplication using the generalized matrix multiplication algorithm comprises using node masks for memory buffers shared by the plurality of processing nodes.
11. An apparatus comprising:
at least one hardware processor; and
a memory to store instructions that, when executed by the at least one hardware processor, cause the at least one hardware processor to:
partition matrices associated with a matrix multiplication into a plurality of partitions that corresponds to a plurality of processor sockets;
size the plurality of partitions based on first costs corresponding to candidate matrix decompositions to provide a plurality of sized partitions, wherein a given first cost of the first costs is based on a first comparative analysis of first block sizes of the corresponding candidate matrix decomposition along a first dimension and second block sizes of the corresponding candidate matrix decomposition along a second dimension;
assign the plurality of sized partitions to the plurality of processor sockets in a manner that a given set of sized partitions of the plurality of sized partitions is assigned to a given processor socket of the plurality of processor sockets;
for the given set of sized partitions, subdivide the partitions of the given set based on second costs corresponding to candidate matrix sub-decompositions to provide a plurality of sized sub-partitions, wherein a given second cost of the second costs is based on a second comparative analysis of first sub-block sizes of the corresponding candidate matrix sub-decomposition along the first dimension and second sub-block sizes of the corresponding candidate matrix sub-decomposition along the second dimension; and
assign the plurality of sized sub-partitions to a plurality of processing nodes of the given processor socket for performing processing of the multiplication.
12. The apparatus of claim 11 , wherein the instructions, when executed by the at least one hardware processor, further cause the at least one hardware processor to:
based on a processing core per processing node number, identify a plurality of candidate processing thread-to-processing core assignments;
based on at least one of a cache block size and a processor core per last level cache number, select a given candidate processing thread-to-processing core assignment of the plurality of candidate processing thread-to-processing core assignments; and
assign threads to each processing node of the plurality of processing nodes based on the given candidate processing thread-to-processing core assignment.
13. The apparatus of claim 12 , wherein the instructions, when executed by the at least one hardware processor, further cause the at least one hardware processor to:
process the multiplication using a generalized matrix multiplication algorithm based on the assigned plurality of sized partitions, the plurality of sized sub-partitions and the assigned threads.
14. The apparatus of claim 13 , wherein processing the multiplication using the generalized matrix multiplication algorithm comprises using synchronization barriers in the threads.
15. The apparatus of claim 13 , wherein processing the multiplication using the generalized matrix multiplication algorithm comprises using node masks for memory buffers shared by the plurality of processing nodes.